Details for: grm31cr61e106ka12l

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GRM31CR61E106KA12L
CAPACITOR, CERAMIC, MULTILAYER, 25 V, X5R, 10 uF, SURFACE MOUNT, 1206, CHIP, ROHS COMPLIANT

Reference Designs

  • High Power Density Voltage Regulator Module for CPU Core Power in Enterprise Switching
    PMP7935: The PMP7935 is a single-phase synchronous buck converter module rated for 0.9V output at 45A from an input voltage of 12V. It is used for CPU core power in an enterprise network switching application. The small 1.1"x0.65" module delivers 90% peak efficiency and is smaller and less costly than equivalent multi-phase designs. This modular solution lends itself well to data center equipment where heat generation is increasingly expensive and a high power density is required.
  • Non-Synchronous Flyback Converter with an Isolated Output
    PMP7899: PMP7899 is a Non-Synchronous Flyback converter with 8 volts to 18 volts input and a 1500VRMS isolated output at 48 volts at 1 Amp continuous.
  • Altera Arria V FPGA Power Supply Reference Design
    PMP9357.1: This reference design provides all the power supply rails necessary to power Altera's Arria V FPGA. This design uses the TPS54620 to generate the rails to power the FPGA.
  • Altera Arria V FPGA Power Supply Reference Design
    PMP9357.2: This reference design provides all the power supply rails necessary to power Altera's Arria V FPGA. This design uses the TPS54620 to generate the rails to power the FPGA.
  • Altera Arria V FPGA Power Supply Reference Design
    PMP9357.3: This reference design provides all the power supply rails necessary to power Altera's Arria V FPGA. This design uses the TPS54620 to generate the rails to power the FPGA.
  • Altera Arria V FPGA Power Supply Reference Design
    PMP9357.4: This reference design provides all the power supply rails necessary to power Altera's Arria V FPGA. This design uses the TPS54620 to generate the rails to power the FPGA.
  • Altera Arria V FPGA Power Supply Reference Design
    PMP9357.5: This reference design provides all the power supply rails necessary to power Altera's Arria V FPGA. This design uses the TPS54620 to generate the rails to power the FPGA.
  • Altera Arria V FPGA Power Supply Reference Design
    PMP9357.6: This reference design provides all the power supply rails necessary to power Altera's Arria V FPGA. This design uses the TPS54620 to generate the rails to power the FPGA.
  • JESD204B Link Latency Design Using a High Speed ADC
    TIDA-00153: JESD204B links are the latest trend in data-converter digital interfaces. These links take advantage of high-speed serial-digital technology to offer many compelling benefits including improved channel densities. This reference design addresses one of the challenges of adopting the new interface: understanding and designing the link latency. An example achieves deterministic latency and determines the link latency of a system containing the Texas Instruments LM97937 ADC and Xilinx Kintex 7 FPGA.
  • Altera Arria V GZ FPGA Discrete Power Solution Reference Design
    PMP9357: The PMP9357 reference design is a complete power solution for Altera's Arria V series FPGAs. This design uses several TPS54620 synchronous step down converters, LDOs, and a DDR termination regulator to provide all the necessary rails to power the FPGA. To provide correct power sequencing, a UCD90120A power supply sequencer/monitor is used and can be controlled through I2C.
  • Dual-Wideband RF-to-Digital Receiver Design
    TIDA-00073: The TSW1265EVM is an example design of a wideband RF to digital dual receiver solution capable of digitizing up to 125MHz of spectrum. The system provides a reference on how to use the ADS4249, LMH6521, LMK0480x, and a dual mixer to achieve this. This reference EVEM coupled with a capture card such as the TSW1400 can be used to capture and analyze narrow band and wideband signals. Instructions are provided on how to change the LO and IF frequencies for different application needs. The TIDA-00073 was implemented with hardware from the TSW1265EVM.
  • Wideband RF-to-Digital Complex Receiver-Feedback Signal Chain
    TIDA-00074: This is a wideband complex-receiver reference design and evaluation platform that is ideally suited for use as a feedback receiver for transmitter digital predistortion. The EVM signal chain is ideal for high intermediate-frequency (IF) complex-feedback applications and contains a complex demodulator, TI?s LMH6521 dual-channel DVGA and ADS5402 12-bit 800-MSPS dual-channel ADC. By modifying the onboard filter components, the signal chain is configurable for a variety of frequency plans. The EVM also includes TI?s LMK04808 dual-PLL clock jitter cleaner and generator to provide an onboard low-noise clocking solution. The LMH6521 DVGA gain is controlled through the GUI or alternatively through the high speed connector with an FPGA.
  • 100V-400Vdc Input, 15V/25mA Auxillary Supply Reference Design
    PMP10338: This reference design generates a non-isolated 15V/25mA output from a 100V-400V DC input. It is intended to be used as an auxillary bias supply in off-line applications. It can be connected directly to the bulk input cap, after the bridge rectifier in most AC/DC system. The UCC28910 with integrated 700V MOSFET controls a simple flyback converter power stage. The variable switching frequency control method and valley switching of the UCC28910 reduce losses. This highly integrated design consumes very little board space and is comprised of only 13 components.
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CAP 10UF 25VDC X5R 10% SMD 1206 - Cut TR (SOS)

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