74LS240N vs DM54LS240J feature comparison

74LS240N NXP Semiconductors

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DM54LS240J Fairchild Semiconductor Corporation

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Part Life Cycle Code Obsolete Obsolete
Ihs Manufacturer SIGNETICS CORP FAIRCHILD SEMICONDUCTOR CORP
Part Package Code DIP DIP
Package Description DIP, DIP, DIP20,.3
Pin Count 20 20
Reach Compliance Code unknown unknown
Family LS LS
JESD-30 Code R-PDIP-T20 R-GDIP-T20
Logic IC Type BUS DRIVER BUS DRIVER
Number of Bits 4 4
Number of Functions 2 2
Number of Ports 2 2
Number of Terminals 20 20
Operating Temperature-Max 70 °C 125 °C
Operating Temperature-Min -55 °C
Output Characteristics 3-STATE 3-STATE
Output Polarity INVERTED INVERTED
Package Body Material PLASTIC/EPOXY CERAMIC, GLASS-SEALED
Package Code DIP DIP
Package Shape RECTANGULAR RECTANGULAR
Package Style IN-LINE IN-LINE
Propagation Delay (tpd) 18 ns 18 ns
Qualification Status Not Qualified Not Qualified
Supply Voltage-Max (Vsup) 5.25 V 5.5 V
Supply Voltage-Min (Vsup) 4.75 V 4.5 V
Supply Voltage-Nom (Vsup) 5 V 5 V
Surface Mount NO NO
Technology TTL TTL
Temperature Grade COMMERCIAL MILITARY
Terminal Form THROUGH-HOLE THROUGH-HOLE
Terminal Position DUAL DUAL
Base Number Matches 3 4
Rohs Code No
HTS Code 8542.39.00.01
Control Type ENABLE LOW
JESD-609 Code e0
Max I(ol) 0.012 A
Package Equivalence Code DIP20,.3
Power Supply Current-Max (ICC) 50 mA
Prop. Delay@Nom-Sup 18 ns
Seated Height-Max 5.08 mm
Terminal Finish TIN LEAD
Terminal Pitch 2.54 mm
Width 7.62 mm

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