CD54HCT00F3A
vs
74HC132D-Q100
feature comparison
| Rohs Code |
No
|
Yes
|
| Part Life Cycle Code |
Transferred
|
Transferred
|
| Ihs Manufacturer |
HARRIS SEMICONDUCTOR
|
NXP SEMICONDUCTORS
|
| Package Description |
DIP, DIP14,.3
|
SOP,
|
| Reach Compliance Code |
unknown
|
unknown
|
| HTS Code |
8542.39.00.01
|
8542.39.00.01
|
| Family |
HCT
|
HC/UH
|
| JESD-30 Code |
R-GDIP-T14
|
R-PDSO-G14
|
| JESD-609 Code |
e0
|
e4
|
| Load Capacitance (CL) |
50 pF
|
|
| Logic IC Type |
NAND GATE
|
NAND GATE
|
| Max I(ol) |
0.004 A
|
|
| Number of Functions |
4
|
4
|
| Number of Inputs |
2
|
2
|
| Number of Terminals |
14
|
14
|
| Operating Temperature-Max |
125 °C
|
125 °C
|
| Operating Temperature-Min |
-55 °C
|
-40 °C
|
| Package Body Material |
CERAMIC, GLASS-SEALED
|
PLASTIC/EPOXY
|
| Package Code |
DIP
|
SOP
|
| Package Equivalence Code |
DIP14,.3
|
|
| Package Shape |
RECTANGULAR
|
RECTANGULAR
|
| Package Style |
IN-LINE
|
SMALL OUTLINE
|
| Prop. Delay@Nom-Sup |
30 ns
|
|
| Qualification Status |
Not Qualified
|
|
| Schmitt Trigger |
NO
|
|
| Screening Level |
38535Q/M;38534H;883B
|
AEC-Q100
|
| Supply Voltage-Max (Vsup) |
5.5 V
|
6 V
|
| Supply Voltage-Min (Vsup) |
4.5 V
|
2 V
|
| Supply Voltage-Nom (Vsup) |
5 V
|
5 V
|
| Surface Mount |
NO
|
YES
|
| Technology |
CMOS
|
CMOS
|
| Temperature Grade |
MILITARY
|
AUTOMOTIVE
|
| Terminal Finish |
Tin/Lead (Sn/Pb)
|
Nickel/Palladium/Gold (Ni/Pd/Au)
|
| Terminal Form |
THROUGH-HOLE
|
GULL WING
|
| Terminal Pitch |
2.54 mm
|
1.27 mm
|
| Terminal Position |
DUAL
|
DUAL
|
| Base Number Matches |
4
|
2
|
| Part Package Code |
|
SOIC
|
| Pin Count |
|
14
|
| Length |
|
8.65 mm
|
| Moisture Sensitivity Level |
|
1
|
| Peak Reflow Temperature (Cel) |
|
NOT SPECIFIED
|
| Propagation Delay (tpd) |
|
190 ns
|
| Seated Height-Max |
|
1.75 mm
|
| Time@Peak Reflow Temperature-Max (s) |
|
NOT SPECIFIED
|
| Width |
|
3.9 mm
|
|
|
|
Compare 74HC132D-Q100 with alternatives