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CD54HCT132F/3 Harris SemiconductorBuy Now Datasheet |
CD74HC132EE4 Texas InstrumentsBuy Now Datasheet |
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| Part Life Cycle Code | Obsolete | Active |
| Package Description | , | DIP, DIP14,.3 |
| Reach Compliance Code | unknown | compliant |
| HTS Code | 8542.39.00.01 | 8542.39.00.01 |
| Family | HCT | HC |
| JESD-30 Code | R-CDIP-T14 | R-PDIP-T14 |
| Logic IC Type | NAND GATE | NAND GATE |
| Number of Functions | 4 | 4 |
| Number of Inputs | 2 | 2 |
| Number of Terminals | 14 | 14 |
| Operating Temperature-Max | 125 °C | 125 °C |
| Operating Temperature-Min | -55 °C | -55 °C |
| Package Body Material | CERAMIC, METAL-SEALED COFIRED | PLASTIC/EPOXY |
| Package Shape | RECTANGULAR | RECTANGULAR |
| Package Style | IN-LINE | IN-LINE |
| Propagation Delay (tpd) | 50 ns | 188 ns |
| Qualification Status | Not Qualified | Not Qualified |
| Supply Voltage-Max (Vsup) | 5.5 V | 6 V |
| Supply Voltage-Min (Vsup) | 4.5 V | 2 V |
| Supply Voltage-Nom (Vsup) | 5 V | 4.5 V |
| Surface Mount | NO | NO |
| Technology | CMOS | CMOS |
| Temperature Grade | MILITARY | MILITARY |
| Terminal Form | THROUGH-HOLE | THROUGH-HOLE |
| Terminal Position | DUAL | DUAL |
| Base Number Matches | 3 | 1 |
| Source Content uid | CD74HC132EE4 | |
| Rohs Code | Yes | |
| Part Package Code | DIP | |
| Pin Count | 14 | |
| Factory Lead Time | 6 Weeks | |
| JESD-609 Code | e4 | |
| Length | 19.305 mm | |
| Load Capacitance (CL) | 50 pF | |
| Max I(ol) | 0.0052 A | |
| Package Code | DIP | |
| Package Equivalence Code | DIP14,.3 | |
| Packing Method | TUBE | |
| Peak Reflow Temperature (Cel) | NOT SPECIFIED | |
| Power Supplies | 2/6 V | |
| Power Supply Current-Max (ICC) | 0.04 mA | |
| Prop. Delay@Nom-Sup | 38 ns | |
| Schmitt Trigger | YES | |
| Seated Height-Max | 5.08 mm | |
| Terminal Finish | Nickel/Palladium/Gold (Ni/Pd/Au) | |
| Terminal Pitch | 2.54 mm | |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED | |
| Width | 7.62 mm | |
