CY7C346B-25RC vs CY7C342B-25RI feature comparison

CY7C346B-25RC Cypress Semiconductor

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CY7C342B-25RI Cypress Semiconductor

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Rohs Code No
Part Life Cycle Code Obsolete Obsolete
Ihs Manufacturer CYPRESS SEMICONDUCTOR CORP CYPRESS SEMICONDUCTOR CORP
Part Package Code PGA PGA
Package Description WINDOWED, CERAMIC, PGA-100 WPGA, PGA68,11X11
Pin Count 100 68
Reach Compliance Code not_compliant compliant
HTS Code 8542.39.00.01 8542.39.00.01
Additional Feature LABS INTERCONNECTED BY PIA; 8 LABS; 128 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK LABS INTERCONNECTED BY PIA; 8 LABS; 128 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK
Clock Frequency-Max 62.5 MHz 62.5 MHz
In-System Programmable NO NO
JESD-30 Code S-CPGA-P100 S-CPGA-P68
JESD-609 Code e0
JTAG BST NO NO
Length 33.3375 mm 27.94 mm
Number of Dedicated Inputs 19 7
Number of I/O Lines 64 52
Number of Macro Cells 128 128
Number of Terminals 100 68
Operating Temperature-Max 70 °C 85 °C
Operating Temperature-Min -40 °C
Organization 19 DEDICATED INPUTS, 64 I/O 7 DEDICATED INPUTS, 52 I/O
Output Function MACROCELL MACROCELL
Package Body Material CERAMIC, METAL-SEALED COFIRED CERAMIC, METAL-SEALED COFIRED
Package Code WPGA WPGA
Package Equivalence Code PGA100M,13X13 PGA68,11X11
Package Shape SQUARE SQUARE
Package Style GRID ARRAY, WINDOW GRID ARRAY, WINDOW
Programmable Logic Type UV PLD UV PLD
Propagation Delay 40 ns 40 ns
Qualification Status Not Qualified Not Qualified
Seated Height-Max 5.715 mm 5.715 mm
Supply Voltage-Max 5.25 V 5.5 V
Supply Voltage-Min 4.75 V 4.5 V
Supply Voltage-Nom 5 V 5 V
Surface Mount NO NO
Technology CMOS CMOS
Temperature Grade COMMERCIAL INDUSTRIAL
Terminal Finish TIN LEAD
Terminal Form PIN/PEG PIN/PEG
Terminal Pitch 2.54 mm 2.54 mm
Terminal Position PERPENDICULAR PERPENDICULAR
Width 33.3375 mm 27.94 mm
Base Number Matches 1 1

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