EP320DC-2 vs PLDC18G8L-15WC feature comparison

EP320DC-2 Altera Corporation

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PLDC18G8L-15WC Cypress Semiconductor

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Pbfree Code No
Rohs Code No No
Part Life Cycle Code Obsolete Obsolete
Ihs Manufacturer ALTERA CORP CYPRESS SEMICONDUCTOR CORP
Part Package Code DIP DIP
Package Description WDIP, DIP20,.3 0.300 INCH, WINDOWED, CERDIP-20
Pin Count 20 20
Reach Compliance Code unknown compliant
HTS Code 8542.39.00.01 8542.39.00.01
Additional Feature 8 MACROCELLS; SHARED INPUT/CLOCK PAL WITH MACROCELLS; 8 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK
Architecture PAL-TYPE PAL-TYPE
Clock Frequency-Max 40 MHz 41.6 MHz
JESD-30 Code R-GDIP-T20 R-GDIP-T20
JESD-609 Code e0 e0
Length 24.003 mm 24.13 mm
Number of Dedicated Inputs 9 8
Number of I/O Lines 8 8
Number of Inputs 18 18
Number of Outputs 8 8
Number of Product Terms 72 72
Number of Terminals 20 20
Operating Temperature-Max 70 °C 75 °C
Operating Temperature-Min
Organization 9 DEDICATED INPUTS, 8 I/O 8 DEDICATED INPUTS, 8 I/O
Output Function MACROCELL MACROCELL
Package Body Material CERAMIC, GLASS-SEALED CERAMIC, GLASS-SEALED
Package Code WDIP WDIP
Package Equivalence Code DIP20,.3 DIP20,.3
Package Shape RECTANGULAR RECTANGULAR
Package Style IN-LINE, WINDOW IN-LINE, WINDOW
Peak Reflow Temperature (Cel) 220
Programmable Logic Type UV PLD UV PLD
Propagation Delay 35 ns 15 ns
Qualification Status Not Qualified Not Qualified
Seated Height-Max 4.826 mm 5.08 mm
Supply Voltage-Max 5.25 V 5.25 V
Supply Voltage-Min 4.75 V 4.75 V
Supply Voltage-Nom 5 V 5 V
Surface Mount NO NO
Technology CMOS CMOS
Temperature Grade COMMERCIAL COMMERCIAL EXTENDED
Terminal Finish TIN LEAD Tin/Lead (Sn/Pb)
Terminal Form THROUGH-HOLE THROUGH-HOLE
Terminal Pitch 2.54 mm 2.54 mm
Terminal Position DUAL DUAL
Width 7.62 mm 7.62 mm
Base Number Matches 1 1

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