EP910PC-30 vs DPLD910-25 feature comparison

EP910PC-30 Texas Instruments

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DPLD910-25 Intel Corporation

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Rohs Code No No
Part Life Cycle Code Obsolete Obsolete
Ihs Manufacturer TEXAS INSTRUMENTS INC INTEL CORP
Package Description DIP-40 WDIP, DIP40,.6
Reach Compliance Code not_compliant compliant
HTS Code 8542.39.00.01 8542.39.00.01
Additional Feature 24 MACROCELL; CONFIGURABLE I/O PAL WITH MACROCELLS; 24 MACROCELLS; 2 EXTERNAL CLOCKS; ASYNCHRONOUS CLOCKS
Architecture PAL-TYPE PAL-TYPE
Clock Frequency-Max 33.3 MHz 27.7 MHz
JESD-30 Code R-PDIP-T40 R-GDIP-T40
Number of Dedicated Inputs 12 12
Number of I/O Lines 24 24
Number of Inputs 36 36
Number of Outputs 24 24
Number of Product Terms 240 240
Number of Terminals 40 40
Operating Temperature-Max 70 °C 70 °C
Operating Temperature-Min
Organization 12 DEDICATED INPUTS, 24 I/O 12 DEDICATED INPUTS, 24 I/O
Output Function MACROCELL MACROCELL
Package Body Material PLASTIC/EPOXY CERAMIC, GLASS-SEALED
Package Code DIP WDIP
Package Equivalence Code DIP40,.6 DIP40,.6
Package Shape RECTANGULAR RECTANGULAR
Package Style IN-LINE IN-LINE, WINDOW
Peak Reflow Temperature (Cel) NOT SPECIFIED
Programmable Logic Type OT PLD UV PLD
Propagation Delay 33 ns 28 ns
Qualification Status Not Qualified Not Qualified
Supply Voltage-Max 5.25 V 5.25 V
Supply Voltage-Min 4.75 V 4.75 V
Supply Voltage-Nom 5 V 5 V
Surface Mount NO NO
Technology CMOS CMOS
Temperature Grade COMMERCIAL COMMERCIAL
Terminal Form THROUGH-HOLE THROUGH-HOLE
Terminal Pitch 2.54 mm 2.54 mm
Terminal Position DUAL DUAL
Time@Peak Reflow Temperature-Max (s) NOT SPECIFIED
Base Number Matches 1 2
Part Package Code DIP
Pin Count 40
JESD-609 Code e0
Length 52.325 mm
Seated Height-Max 5.72 mm
Terminal Finish TIN LEAD
Width 15.24 mm

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