GAL20V8QS-20LNC
vs
GAL20V8A-15VC
feature comparison
| Rohs Code |
No
|
No
|
| Part Life Cycle Code |
Obsolete
|
Obsolete
|
| Ihs Manufacturer |
NATIONAL SEMICONDUCTOR CORP
|
NATIONAL SEMICONDUCTOR CORP
|
| Package Description |
0.300 INCH, SKINNY, PLASTIC, DIP-24
|
QCCJ, LDCC28,.5SQ
|
| Reach Compliance Code |
unknown
|
unknown
|
| Additional Feature |
8 MACROCELLS; SHARED INPUT/CLOCK; REGISTER PRELOAD
|
POWER-UP RESET; REGISTER PRELOAD
|
| Architecture |
PAL-TYPE
|
PAL-TYPE
|
| Clock Frequency-Max |
37 MHz
|
41.6 MHz
|
| JESD-30 Code |
R-PDIP-T24
|
S-PQCC-J28
|
| JESD-609 Code |
e0
|
e0
|
| Length |
31.915 mm
|
11.43 mm
|
| Number of Dedicated Inputs |
12
|
12
|
| Number of I/O Lines |
8
|
8
|
| Number of Inputs |
20
|
20
|
| Number of Outputs |
8
|
8
|
| Number of Product Terms |
64
|
64
|
| Number of Terminals |
24
|
28
|
| Operating Temperature-Max |
75 °C
|
75 °C
|
| Operating Temperature-Min |
|
|
| Organization |
12 DEDICATED INPUTS, 8 I/O
|
12 DEDICATED INPUTS, 8 I/O
|
| Output Function |
MACROCELL
|
MACROCELL
|
| Package Body Material |
PLASTIC/EPOXY
|
PLASTIC/EPOXY
|
| Package Code |
DIP
|
QCCJ
|
| Package Equivalence Code |
DIP24,.3
|
LDCC28,.5SQ
|
| Package Shape |
RECTANGULAR
|
SQUARE
|
| Package Style |
IN-LINE
|
CHIP CARRIER
|
| Programmable Logic Type |
EE PLD
|
EE PLD
|
| Propagation Delay |
20 ns
|
15 ns
|
| Qualification Status |
Not Qualified
|
Not Qualified
|
| Seated Height-Max |
5.08 mm
|
4.57 mm
|
| Supply Voltage-Max |
5.25 V
|
5.25 V
|
| Supply Voltage-Min |
4.75 V
|
4.75 V
|
| Supply Voltage-Nom |
5 V
|
5 V
|
| Surface Mount |
NO
|
YES
|
| Technology |
CMOS
|
CMOS
|
| Temperature Grade |
COMMERCIAL EXTENDED
|
COMMERCIAL EXTENDED
|
| Terminal Finish |
Tin/Lead (Sn/Pb)
|
TIN LEAD
|
| Terminal Form |
THROUGH-HOLE
|
J BEND
|
| Terminal Pitch |
2.54 mm
|
1.27 mm
|
| Terminal Position |
DUAL
|
QUAD
|
| Width |
7.62 mm
|
11.43 mm
|
| Base Number Matches |
1
|
1
|
| HTS Code |
|
8542.39.00.01
|
|
|
|
Compare GAL20V8QS-20LNC with alternatives
Compare GAL20V8A-15VC with alternatives