PA7140P-25 vs EP910IDC40-15 feature comparison

PA7140P-25 Integrated Circuit Technology Corp

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EP910IDC40-15 Altera Corporation

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Rohs Code No No
Part Life Cycle Code Obsolete Obsolete
Ihs Manufacturer INTEGRATED CIRCUIT TECHNOLOGY CORP ALTERA CORP
Part Package Code DIP DIP
Package Description DIP, DIP40,.6 WDIP, DIP40,.6
Pin Count 40 40
Reach Compliance Code unknown compliant
HTS Code 8542.39.00.01 8542.39.00.01
Clock Frequency-Max 62.5 MHz 100 MHz
JESD-30 Code R-PDIP-T40 R-GDIP-T40
JESD-609 Code e0 e0
Length 52.07 mm 52.07 mm
Number of Dedicated Inputs 12 12
Number of I/O Lines 24 24
Number of Inputs 38 36
Number of Outputs 24 24
Number of Terminals 40 40
Operating Temperature-Max 70 °C 70 °C
Operating Temperature-Min
Organization 12 DEDICATED INPUTS, 24 I/O 12 DEDICATED INPUTS, 24 I/O
Output Function COMBINATORIAL MACROCELL
Package Body Material PLASTIC/EPOXY CERAMIC, GLASS-SEALED
Package Code DIP WDIP
Package Equivalence Code DIP40,.6 DIP40,.6
Package Shape RECTANGULAR RECTANGULAR
Package Style IN-LINE IN-LINE, WINDOW
Programmable Logic Type EE PLD UV PLD
Propagation Delay 25 ns 15 ns
Qualification Status Not Qualified Not Qualified
Supply Voltage-Max 5.25 V 5.25 V
Supply Voltage-Min 4.75 V 4.75 V
Supply Voltage-Nom 5 V 5 V
Surface Mount NO NO
Technology CMOS CMOS
Temperature Grade COMMERCIAL COMMERCIAL
Terminal Finish Tin/Lead (Sn/Pb) TIN LEAD
Terminal Form THROUGH-HOLE THROUGH-HOLE
Terminal Pitch 2.54 mm 2.54 mm
Terminal Position DUAL DUAL
Width 15.24 mm 15.24 mm
Base Number Matches 1 1
Additional Feature 24 MACROCELLS; 2 EXTERNAL CLOCKS
Architecture PAL-TYPE
Number of Product Terms 240
Peak Reflow Temperature (Cel) 220
Seated Height-Max 5.75 mm

Compare PA7140P-25 with alternatives

Compare EP910IDC40-15 with alternatives