PDTA115EEF vs PDTA115ET,215 feature comparison

PDTA115EEF Nexperia

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PDTA115ET,215 NXP Semiconductors

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Part Life Cycle Code Active Transferred
Ihs Manufacturer NEXPERIA NXP SEMICONDUCTORS
Package Description SMALL OUTLINE, R-PDSO-F3 PLASTIC PACKAGE-3
Reach Compliance Code compliant compliant
ECCN Code EAR99 EAR99
Date Of Intro 2017-02-01
Additional Feature BUILT-IN BIAS RESISTOR RATIO IS 1 BUILT-IN BIAS RESISTOR RATIO IS 1
Collector Current-Max (IC) 0.02 A 0.02 A
Collector-Emitter Voltage-Max 50 V 50 V
Configuration SINGLE WITH BUILT-IN RESISTOR SINGLE WITH BUILT-IN RESISTOR
DC Current Gain-Min (hFE) 80 80
JESD-30 Code R-PDSO-F3 R-PDSO-G3
Number of Elements 1 1
Number of Terminals 3 3
Package Body Material PLASTIC/EPOXY PLASTIC/EPOXY
Package Shape RECTANGULAR RECTANGULAR
Package Style SMALL OUTLINE SMALL OUTLINE
Polarity/Channel Type PNP PNP
Surface Mount YES YES
Terminal Form FLAT GULL WING
Terminal Position DUAL DUAL
Transistor Application SWITCHING SWITCHING
Transistor Element Material SILICON SILICON
Base Number Matches 3 2
Rohs Code Yes
Part Package Code TO-236
Pin Count 3
Manufacturer Package Code SOT23
Factory Lead Time 4 Weeks
JEDEC-95 Code TO-236AB
JESD-609 Code e3
Moisture Sensitivity Level 1
Operating Temperature-Max 150 °C
Peak Reflow Temperature (Cel) 260
Power Dissipation-Max (Abs) 0.25 W
Qualification Status Not Qualified
Terminal Finish TIN
Time@Peak Reflow Temperature-Max (s) 30

Compare PDTA115EEF with alternatives

Compare PDTA115ET,215 with alternatives