XQVR1000-4CG560M vs XQV1000-4CGG560Q feature comparison

XQVR1000-4CG560M AMD Xilinx

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XQV1000-4CGG560Q AMD Xilinx

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Rohs Code No Yes
Part Life Cycle Code Obsolete Transferred
Ihs Manufacturer XILINX INC XILINX INC
Part Package Code CGA CGA
Package Description HEAT SINK, CERAMIC, CGA-560 CERAMIC, CGA-560
Pin Count 560 560
Reach Compliance Code unknown compliant
ECCN Code 3A001.A.2.C 3A001.A.2.C
HTS Code 8542.39.00.01 8542.39.00.01
JESD-30 Code S-CBGA-X560 S-CBGA-X560
Length 42.5 mm 42.5 mm
Number of CLBs 6144 6144
Number of Equivalent Gates 1124022 1124022
Number of Inputs 404
Number of Logic Cells 27648 27648
Number of Outputs 404
Number of Terminals 560 560
Operating Temperature-Max 125 °C 125 °C
Operating Temperature-Min -55 °C -55 °C
Organization 6144 CLBS, 1124022 GATES 6144 CLBS, 1124022 GATES
Package Body Material CERAMIC, METAL-SEALED COFIRED CERAMIC, METAL-SEALED COFIRED
Package Code HCGA HCGA
Package Equivalence Code CGA560,33X33,50 CGA560,33X33,50
Package Shape SQUARE SQUARE
Package Style GRID ARRAY, HEAT SINK/SLUG GRID ARRAY, HEAT SINK/SLUG
Peak Reflow Temperature (Cel) NOT SPECIFIED
Programmable Logic Type FIELD PROGRAMMABLE GATE ARRAY FIELD PROGRAMMABLE GATE ARRAY
Qualification Status Not Qualified Not Qualified
Seated Height-Max 4.9 mm 4.9 mm
Supply Voltage-Max 2.625 V 2.625 V
Supply Voltage-Min 2.375 V 2.375 V
Supply Voltage-Nom 2.5 V 2.5 V
Surface Mount YES YES
Technology CMOS CMOS
Temperature Grade MILITARY MILITARY
Terminal Form UNSPECIFIED UNSPECIFIED
Terminal Pitch 1.27 mm 1.27 mm
Terminal Position BOTTOM BOTTOM
Time@Peak Reflow Temperature-Max (s) NOT SPECIFIED
Total Dose 100k Rad(Si) V
Width 42.5 mm 42.5 mm
Base Number Matches 1 1
Pbfree Code Yes
Combinatorial Delay of a CLB-Max 0.8 ns
JESD-609 Code e3
Screening Level MIL-PRF-38535 Class Q
Terminal Finish MATTE TIN

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Compare XQV1000-4CGG560Q with alternatives