Datasheets
74AUP1G58FHX by:

Two-Input, Low Power, Universal Configurable Logic Gate, 6LD,MICROPAK2,JEDEC MO252,1.0MM SQUARE,.35MM PITCH, 5000/TAPE REEL

Part Details for 74AUP1G58FHX by Fairchild Semiconductor Corporation

Overview of 74AUP1G58FHX by Fairchild Semiconductor Corporation

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Applications Consumer Electronics Education and Research Financial Technology (Fintech) Computing and Data Storage Healthcare Medical Imaging

Price & Stock for 74AUP1G58FHX

Part # Distributor Description Stock Price Buy
DISTI # 2156-74AUP1G58FHX-ND
DigiKey TWO-INPUT, LOW POWER, UNIVERSAL Min Qty: 1507 Container: Bulk MARKETPLACE PRODUCT 284650
In Stock
  • 1,507 $0.2000
$0.2000 Buy Now
Rochester Electronics Two-Input, Low Power, Universal Configurable Logic Gate RoHS: Compliant Status: Active Min Qty: 1 632703
  • 1 $0.2011
  • 25 $0.1971
  • 100 $0.1890
  • 500 $0.1810
  • 1,000 $0.1709
$0.1709 / $0.2011 Buy Now
Sense Electronic Company Limited DFN 4200
RFQ

Part Details for 74AUP1G58FHX

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74AUP1G58FHX Part Data Attributes

74AUP1G58FHX Fairchild Semiconductor Corporation
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74AUP1G58FHX Fairchild Semiconductor Corporation Two-Input, Low Power, Universal Configurable Logic Gate, 6LD,MICROPAK2,JEDEC MO252,1.0MM SQUARE,.35MM PITCH, 5000/TAPE REEL
Pbfree Code Yes
Rohs Code Yes
Part Life Cycle Code Transferred
Ihs Manufacturer FAIRCHILD SEMICONDUCTOR CORP
Part Package Code MICROPAK2
Package Description 1 X 1 MM, 0.35 MM PITCH, MO-252, MICRO PACKAGE-6
Pin Count 6
Manufacturer Package Code 6LD,MICROPAK2,JEDEC MO252,1.0MM SQUARE,.35MM PITCH
Reach Compliance Code compliant
ECCN Code EAR99
HTS Code 8542.39.00.01
Family AUP/ULP/V
JESD-30 Code S-PDSO-N6
JESD-609 Code e4
Length 1 mm
Load Capacitance (CL) 30 pF
Logic IC Type LOGIC CIRCUIT
Max I(ol) 0.0011 A
Moisture Sensitivity Level 1
Number of Functions 1
Number of Terminals 6
Operating Temperature-Max 85 °C
Operating Temperature-Min -40 °C
Package Body Material PLASTIC/EPOXY
Package Code VSON
Package Equivalence Code SOLCC6,.04,14
Package Shape SQUARE
Package Style SMALL OUTLINE, VERY THIN PROFILE
Packing Method TR
Peak Reflow Temperature (Cel) 260
Prop. Delay@Nom-Sup 19 ns
Qualification Status Not Qualified
Schmitt Trigger YES
Seated Height-Max 0.55 mm
Supply Voltage-Max (Vsup) 3.6 V
Supply Voltage-Min (Vsup) 0.8 V
Supply Voltage-Nom (Vsup) 1.2 V
Surface Mount YES
Technology CMOS
Temperature Grade INDUSTRIAL
Terminal Finish Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal Form NO LEAD
Terminal Pitch 0.35 mm
Terminal Position DUAL
Time@Peak Reflow Temperature-Max (s) 30
Width 1 mm

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