Part Details for 74AUP2G80GF,115 by NXP Semiconductors
Overview of 74AUP2G80GF,115 by NXP Semiconductors
- Distributor Offerings: (2 listings)
- Number of FFF Equivalents: (0 replacements)
- CAD Models: (Request Part)
- Number of Functional Equivalents: (0 options)
- Part Data Attributes: (Available)
- Reference Designs: (Not Available)
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Applications
Consumer Electronics
Price & Stock for 74AUP2G80GF,115
Part # | Distributor | Description | Stock | Price | Buy | |
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DISTI #
2156-74AUP2G80GF115-ND
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DigiKey | IC FF D-TYPE DUAL 1BIT 8XSON Min Qty: 1528 Lead time: 1 Weeks Container: Bulk MARKETPLACE PRODUCT |
5000 In Stock |
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$0.2000 | Buy Now |
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Rochester Electronics | 74AUP2G80GF - D Flip-Flop, AUP/ULP/V Series, 2-Func, Positive Edge Triggered, 1-Bit, Inverted Output, SON-8 ' RoHS: Compliant Status: Obsolete Min Qty: 1 | 5000 |
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$0.1686 / $0.1983 | Buy Now |
Part Details for 74AUP2G80GF,115
74AUP2G80GF,115 CAD Models
74AUP2G80GF,115 Part Data Attributes
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74AUP2G80GF,115
NXP Semiconductors
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Datasheet
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74AUP2G80GF,115
NXP Semiconductors
74AUP2G80 - Low-power dual D-type flip-flop; positive-edge trigger SON 8-Pin
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Rohs Code | Yes | |
Part Life Cycle Code | Transferred | |
Ihs Manufacturer | NXP SEMICONDUCTORS | |
Part Package Code | SON | |
Package Description | 1.35 X 1 MM, 0.50 MM HEIGHT, MO-252, SOT-1089, SON-8 | |
Pin Count | 8 | |
Manufacturer Package Code | SOT1089 | |
Reach Compliance Code | compliant | |
Factory Lead Time | 4 Weeks | |
Family | AUP/ULP/V | |
JESD-30 Code | R-PDSO-N8 | |
JESD-609 Code | e3 | |
Length | 1.35 mm | |
Load Capacitance (CL) | 30 pF | |
Logic IC Type | D FLIP-FLOP | |
Max Frequency@Nom-Sup | 70000000 Hz | |
Max I(ol) | 0.0017 A | |
Moisture Sensitivity Level | 1 | |
Number of Bits | 1 | |
Number of Functions | 2 | |
Number of Terminals | 8 | |
Operating Temperature-Max | 125 °C | |
Operating Temperature-Min | -40 °C | |
Output Polarity | INVERTED | |
Package Body Material | PLASTIC/EPOXY | |
Package Code | VSON | |
Package Equivalence Code | SOLCC8,.04,14 | |
Package Shape | RECTANGULAR | |
Package Style | SMALL OUTLINE, VERY THIN PROFILE | |
Packing Method | TR | |
Peak Reflow Temperature (Cel) | 260 | |
Prop. Delay@Nom-Sup | 27.2 ns | |
Propagation Delay (tpd) | 27.2 ns | |
Qualification Status | Not Qualified | |
Seated Height-Max | 0.5 mm | |
Supply Voltage-Max (Vsup) | 3.6 V | |
Supply Voltage-Min (Vsup) | 0.8 V | |
Supply Voltage-Nom (Vsup) | 1.1 V | |
Surface Mount | YES | |
Technology | CMOS | |
Temperature Grade | AUTOMOTIVE | |
Terminal Finish | TIN | |
Terminal Form | NO LEAD | |
Terminal Pitch | 0.35 mm | |
Terminal Position | DUAL | |
Time@Peak Reflow Temperature-Max (s) | 30 | |
Trigger Type | POSITIVE EDGE | |
Width | 1 mm | |
fmax-Min | 510 MHz |