PMP10709: PMP10709 is a system optimized 50 W power designs for A13 Wireless Charger Transmitter used in automotive system. The design has various front end automotive protections such as Load dump through TVS (ISO pulse testing), Reverse Voltage (Through PFET’s body diode), Battery Disconnect Switch with OVP protection (PFET). PMP10709 is primarily four Switch synchronous Buck – Boost design, which supports wide Input voltage range (7V-20V) and delivers any output from 1V-10V based on DAC output of the A13 Wireless Charger. The DAC output changes from 1V to 3.3V which in turn changes the output voltage from 10V to 1V (on the fly) as needed by the algorithm of A13 wireless charger’s transmitter. This design utilizes best in Class Synchronous four Switch Buck Boost Controller LM5175. The design accepts an input voltage of 7Vin to 20Vin and provides the output of 1V- 10V@5 A. Output current never exceeds 5A to protect the charging Coil. The average current regulation loop of the IC at the output is used for this protection.
PMP10612: The PMP10612 reference design is 4-switch buck-boost converter optimized for military radio applications. The design offers up to 40W output power from 7.5V to 18V input. The design offers an adjustable output voltage range from 5V to 40V, and very low output voltage ripple.
TIDA-00177: The TIDA-00177 reference design is an EMC compliant industrial interface to a two-wire HIPERFACE DSL encoder. Applications include industrial servo drives. The design features a 3.3-V supply RS485 transceiver and line termination and coupling for encoder power over RS485 as per HIPERFACE DSL specification. The design has been tested up to 100m cable length with an integrated cable, where the encoder’s two-wire twisted pair was integrated in the same motor cable. The encoder connector output is protected against over-voltage and short circuit to prevent damage to an encoder or during a cable short. The design features an industrial compliant 24-V input with wide range from 18-36V. A 3.3V I/O connector with logic signals for easy interface to a host processor with HIPERFACE DSL Master IP Core is made available.