Part Details for M2GL090-FG676I by Microchip Technology Inc
Results Overview of M2GL090-FG676I by Microchip Technology Inc
- Distributor Offerings: (5 listings)
- Number of FFF Equivalents: (0 replacements)
- Tariff Estimator: (Available) NEW
- Number of Functional Equivalents: (0 options)
- CAD Models: (Request Part)
- Part Data Attributes: (Available)
- Reference Designs: (Not Available)
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M2GL090-FG676I Information
M2GL090-FG676I by Microchip Technology Inc is a Field Programmable Gate Array.
Field Programmable Gate Arrays are under the broader part category of Programmable Logic Devices.
Programmable Logic Devices (PLDs) are reconfigurable digital components that can be customized for different applications, offering flexibility and improved performance over fixed logic devices. Read more about Programmable Logic Devices on our Programmable Logic part category page.
Price & Stock for M2GL090-FG676I
| Part # | Distributor | Description | Stock | Price | Buy | |
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DISTI #
33AJ8032
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Newark | Igloo2 Low Density Fpga, 86Kles 676 Pbga 27X27X2.44Mm Tray Rohs Compliant: Yes |Microchip M2GL090-FG676I RoHS: Compliant Min Qty: 40 Package Multiple: 1 Date Code: 0 Container: Bulk | 0 |
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$198.0800 / $219.2100 | Buy Now |
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DISTI #
M2GL090-FG676I
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Avnet Americas | FPGA, IGLOO2 M2GL025T, Flash based FPGA, 86184 Logic Cells, 425 I/O, 676-Pin, FPBGA - Trays (Alt: M2GL090-FG676I) COO: Korea (the Republic of) RoHS: Not Compliant Min Qty: 40 Package Multiple: 1 Lead time: 12 Weeks, 0 Days Container: Tray | 0 |
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$205.5125 / $234.8714 | Buy Now |
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DISTI #
M2GL090-FG676I
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Microchip Technology Inc | IGLOO2 Low Density FPGA, 86KLEs, PBGA, Projected EOL: 2049-02-04 COO: South Korea ECCN: 3A991.d RoHS: Compliant Lead time: 12 Weeks, 0 Days Container: Tray | In Stock: 56 and Alternates Available |
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$114.9800 / $234.8700 | Buy Now |
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NAC | IGLOO2 Low Density FPGA, 86KLEs. Package: 676 PBGA 27x27x2.44mm TRAY - FPGA Flash Product Line RoHS: Compliant Min Qty: 40 Package Multiple: 40 Container: Tray | 0 |
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$200.5000 / $234.8700 | Buy Now |
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Chip Stock | FPGA,IGLOO2M2GL025T,FlashbasedFPGA,86184LogicCells,425I/O,676-Pin,FPBGA | 594 |
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RFQ |
US Tariff Estimator: M2GL090-FG676I by Microchip Technology Inc
Calculations from this tool are estimations only for imports into the United States. Please refer to the distributor or manufacturer and reference official US government sources and authorities to verify any final purchase costs.
Part Details for M2GL090-FG676I
M2GL090-FG676I Part Data Attributes
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M2GL090-FG676I
Microchip Technology Inc
Buy Now
Datasheet
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Compare Parts:
M2GL090-FG676I
Microchip Technology Inc
IGLOO2 Low Density FPGA, 86KLEs
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| Rohs Code | No | |
| Part Life Cycle Code | Active | |
| Ihs Manufacturer | MICROCHIP TECHNOLOGY INC | |
| Package Description | FBGA-676 | |
| Pin Count | 676 | |
| Manufacturer Package Code | PBGA-676 | |
| Reach Compliance Code | Compliant | |
| HTS Code | 8542.39.00.01 | |
| Factory Lead Time | 12 Weeks | |
| Samacsys Manufacturer | Microchip | |
| JESD-30 Code | S-PBGA-B676 | |
| JESD-609 Code | e0 | |
| Length | 27 mm | |
| Number of Inputs | 425 | |
| Number of Logic Cells | 86316 | |
| Number of Outputs | 425 | |
| Number of Terminals | 676 | |
| Operating Temperature-Max | 100 °C | |
| Operating Temperature-Min | -40 °C | |
| Package Body Material | PLASTIC/EPOXY | |
| Package Code | BGA | |
| Package Equivalence Code | BGA676,26X26,40 | |
| Package Shape | SQUARE | |
| Package Style | GRID ARRAY | |
| Packing Method | TRAY | |
| Programmable Logic Type | FIELD PROGRAMMABLE GATE ARRAY | |
| Qualification Status | Not Qualified | |
| Seated Height-Max | 2.44 mm | |
| Supply Voltage-Max | 1.26 V | |
| Supply Voltage-Min | 1.14 V | |
| Supply Voltage-Nom | 1.2 V | |
| Surface Mount | YES | |
| Technology | CMOS | |
| Temperature Grade | INDUSTRIAL | |
| Terminal Finish | Tin/Lead (Sn63Pb37) | |
| Terminal Form | BALL | |
| Terminal Pitch | 1 mm | |
| Terminal Position | BOTTOM | |
| Width | 27 mm |
M2GL090-FG676I Frequently Asked Questions (FAQ)
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A 4-layer PCB with a solid ground plane and a separate power plane is recommended. Decoupling capacitors should be placed close to the power pins, and signal traces should be kept short and away from noise sources.
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To optimize power consumption, use the lowest possible voltage and frequency for your design. Also, use the power gating feature to turn off unused blocks, and use the dynamic voltage and frequency scaling (DVFS) feature to adjust power consumption based on system requirements.
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Ensure good airflow around the device, use a heat sink if necessary, and avoid blocking the airflow around the device. Also, use thermal interface materials to improve heat transfer between the device and the heat sink.
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Use a reliable configuration interface such as JTAG or SPI, and ensure that the configuration data is error-free and correctly formatted. Also, use the built-in error detection and correction mechanisms to ensure reliable programming.
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Use controlled impedance traces, and terminate signals properly to minimize reflections. Also, use shielding and grounding techniques to minimize EMI, and ensure that the PCB layout is designed to minimize radiation.