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TPS54327DDAR

Power Circuits » Switching Regulator or Controllers

4.5V to 18V Input, 3-A Synchronous Step-Down Converter 8-SO PowerPAD -40 to 85

Manufacturer Texas Instruments
Price Range $0.5684 / $1.5900

Part Details

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Distributors with Stock

Total Inventory

49,640

FFF Equivalents (1) Functional Equivalents (1)
Part Number Description Manufacturer Compare
TPS54327DDA Power Circuits 4.5V to 18V Input, 3-A Synchronous Step-Down Converter 8-SO PowerPAD -40 to 85 Texas Instruments TPS54327DDAR vs TPS54327DDA
Part Number Description Manufacturer Compare
TPS54327DDA Power Circuits 4.5V to 18V Input, 3-A Synchronous Step-Down Converter 8-SO PowerPAD -40 to 85 Texas Instruments TPS54327DDAR vs TPS54327DDA

Global Popularity

570,434 of 3,262,357 parts

+0.01% change vs. last year

Popularity in Power Circuits

24,639 of 73,489 parts

+0.02% change vs. last year

Popularity in Switching Regulator or Controllers

7,846 of 21,658 parts

+0.02% change vs. last year

Popularity by Region

Very High

Medium

Good

Low

  • 1. China
    100
  • 2. Japan
    95
  • 3. Denmark
    92
  • 4. Thailand
    91
  • 5. Mexico
    83
  • 6. Cayman Islands
    82
  • 7. Jamaica
    81
  • 8. Aruba
    80
  • 9. Slovenia
    78
  • 10. Cambodia
    77

Estimated Price History

Apr 2020 - Present Past 6 Months

price

since last month

Estimated Stock History

Apr 2020 - Present Past 6 Months

Stock

since last month

Market Price Analysis

No data available
Authorized Distributors (6) Independent Distributors (0)

Datasheets & Reference Designs

TPS54327DDAR

Texas Instruments

Reference Designs

  • TIDA-01015 4 GHz Clock Reference Design for 12 Bit High Speed ADCs in Digital Oscilloscopes & Wireless Testers | TI.com
    TIDA-01015: The TIDA-01015 is a clocking solution reference design for high speed direct RF sampling GSPS ADCs. This design showcases the significance of the sampling clock to achieve high SNR for 2nd Nyquist zone input signal frequencies. ADC12J4000 is a 12-bit, 4-GSPS RF sampling ADC with 3-dB input bandwidth of 3.2 GHz capable of capturing signals up to 4 GHz. This design highlights a clocking solution for the ADC12J4000 using TRF3765, to achieve high SNR performance at high input frequencies used in applications such as digital storage oscilloscopes (DSO) and wireless testers.
  • RF Sampling 4-GSPS ADC Reference Design with 8-GHz DC-Coupled Differential Amplifier
    TIDA-00431: Wideband radio frequency (RF) receivers allow greatly increased flexibility in radio designs. The wide instantaneous bandwidth allows flexible tuning without changing hardware and the ability to capture multiple channels at widely separated frequencies. This reference design describes a wideband RF receiver utilizing a 4-GSPS analog-to-digital converter (ADC), with an 8-GHz, DC-coupled, fully differential amplifier front end. The amplifier front end provides signal gain and allows capture of signals down to DC, which is not possible with a balun-coupled input.
  • TIDA-00359 Clocking Solution Reference Design for GSPS ADCs | TI.com
    TIDA-00359: Low cost, high performance clocking solution for GSPS data converters. This reference design discusses the use of a TRF3765, a low noise frequency synthesizer, generating the sampling clock for a 4 GSPS analog-to-digital converter (ADC12J4000). Experiments demonstrate data sheet comparable SNR and SFDR performance.
  • TIDA-00432 Synchronization of JESD204B Giga-Sample ADCs using Xilinx Platform for Phased Array Radar Systems | TI.com
    TIDA-00432: This system level design shows how two ADC12J4000 evaluation modules (EVMs) can be synchronized together using a Xilinx VC707 platform. The design document describes the required hardware modifications and device configurations, including the clocking scheme. Example configuration files are shown for each EVM. The FPGA firmware is described and the relevant Xilinx IP block configuration parameters are shown. Data taken on the actual hardware is shown and analyzed, showing synchronization within 50 ps without characterized cables or calibrated propagation delays.
  • TIDA-00826 50-Ohm 2-GHz Oscilloscope Front-end Reference Design | TI.com
    TIDA-00826: This reference design is part of an analog front-end for 50Ω-input oscilloscope application. System designers can readily use this evaluation platform to process input signals from DC to 2 GHz in both frequency-domain and time-domain applications.
  • Synchronization of JESD204B Giga-Sample ADCs using Xilinx Platform for Phased Array Radar Systems
    TIDA-00432: This system level design shows how two ADC12J4000 evaluation modules (EVMs) can be synchronized together using a Xilinx VC707 platform. The design document describes the required hardware modifications and device configurations, including the clocking scheme. Example configuration files are shown for each EVM. The FPGA firmware is described and the relevant Xilinx IP block configuration parameters are shown. Data taken on the actual hardware is shown and analyzed, showing synchronization within 50 ps without characterized cables or calibrated propagation delays.
  • TIDA-00431 RF Sampling 4-GSPS ADC Reference Design with 8-GHz DC-Coupled Differential Amplifier | TI.com
    TIDA-00431: Wideband radio frequency (RF) receivers allow greatly increased flexibility in radio designs. The wide instantaneous bandwidth allows flexible tuning without changing hardware and the ability to capture multiple channels at widely separated frequencies. This reference design describes a wideband RF receiver utilizing a 4-GSPS analog-to-digital converter (ADC), with an 8-GHz, DC-coupled, fully differential amplifier front end. The amplifier front end provides signal gain and allows capture of signals down to DC, which is not possible with a balun-coupled input.
  • TIDA-01017 High Speed Multi-Channel ADC Clock Reference Design for Oscilloscopes, Wireless Testers and Radars | TI.com
    TIDA-01017: The TIDA-01017 reference design demonstrates the performance of a clocking solution for a high speed multi-channel system, analyzed by measuring the channel to channel skew for the entire input frequency range of the RF sampling ADC. Channel to channel skew is critical for phased array radar and oscilloscope applications. The ADC12J4000 is a low power, 12-bit, 4-GSPS RF-sampling analog to digital converter (ADC) with a buffered analog input, integrated digital down Converter, features a JESD204B interface, and it captures signals up to 4GHz. This design showcases the clocking solution using the LMK04828, to achieve the synchronization between multiple ADC12J4000 signal chains using synchronized SYSREF.
  • Clocking Solution Reference Design for GSPS ADCs
    TIDA-00359: Low cost, high performance clocking solution for GSPS data converters. This reference design discusses the use of a TRF3765, a low noise frequency synthesizer, generating the sampling clock for a 4 GSPS analog-to-digital converter (ADC12J4000). Experiments demonstrate data sheet comparable SNR and SFDR performance.
  • Set Top Box Power Solution
    PMP6638: This reference design is an example of power-trees inside a set-top-box. It performs DC-DC conversions, from 12V supply, for 1.0V/1.2V/1.8V/2.5V/3.3V/5V rails.
  • PMP6638 Set Top Box Power Solution | TI.com
    PMP6638: This reference design is an example of power-trees inside a set-top-box. It performs DC-DC conversions, from 12V supply, for 1.0V/1.2V/1.8V/2.5V/3.3V/5V rails.

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