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PLL clock driver for synch. DRAM & gen. purp. apps w/spread spectrum compatibility, power down mode 8-TSSOP -40 to 85
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HPA00771PWR
Texas Instruments
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HPA00771PWR
Texas Instruments
PLL clock driver for synch. DRAM & gen. purp. apps w/spread spectrum compatibility, power down mode 8-TSSOP -40 to 85
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Rohs Code | No | |
Part Life Cycle Code | Obsolete | |
Ihs Manufacturer | TEXAS INSTRUMENTS INC | |
Package Description | TSSOP, | |
Reach Compliance Code | compliant | |
Samacsys Manufacturer | Texas Instruments | |
Family | CDCV | |
Input Conditioning | STANDARD | |
JESD-30 Code | R-PDSO-G8 | |
JESD-609 Code | e4 | |
Length | 3 mm | |
Load Capacitance (CL) | 25 pF | |
Logic IC Type | PLL BASED CLOCK DRIVER | |
Max I(ol) | 0.012 A | |
Moisture Sensitivity Level | 1 | |
Number of Functions | 1 | |
Number of Inverted Outputs | ||
Number of Terminals | 8 | |
Number of True Outputs | 4 | |
Operating Temperature-Max | 85 °C | |
Operating Temperature-Min | -40 °C | |
Output Characteristics | 3-STATE WITH SERIES RESISTOR | |
Package Body Material | PLASTIC/EPOXY | |
Package Code | TSSOP | |
Package Equivalence Code | TSSOP8,.25 | |
Package Shape | RECTANGULAR | |
Package Style | SMALL OUTLINE, THIN PROFILE, SHRINK PITCH | |
Packing Method | TR | |
Peak Reflow Temperature (Cel) | 260 | |
Prop. Delay@Nom-Sup | 0.15 ns | |
Propagation Delay (tpd) | 0.15 ns | |
Same Edge Skew-Max (tskwd) | 0.15 ns | |
Seated Height-Max | 1.2 mm | |
Supply Voltage-Max (Vsup) | 3.6 V | |
Supply Voltage-Min (Vsup) | 3 V | |
Supply Voltage-Nom (Vsup) | 3.3 V | |
Surface Mount | YES | |
Temperature Grade | INDUSTRIAL | |
Terminal Finish | NICKEL PALLADIUM GOLD | |
Terminal Form | GULL WING | |
Terminal Pitch | 0.65 mm | |
Terminal Position | DUAL | |
Time@Peak Reflow Temperature-Max (s) | 30 | |
Width | 4.4 mm | |
fmax-Min | 200 MHz |