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EE PLD, 5.8ns, 256-Cell, CMOS, PBGA144, 7 X 7 MM, 0.5 MM PITCH, LEAD FREE, CSBGA-144
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Part # | Distributor | Description | Stock | Price | Buy | |
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DISTI #
55AJ0982
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Newark | Ispmach 4000Ze, 1.8V, 256Mc, Zero Power Rohs Compliant: Yes |Lattice Semiconductor LC4256ZE-5MN144C RoHS: Compliant Min Qty: 1800 Package Multiple: 1 Date Code: 0 Container: Bulk | 0 |
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$25.7100 | Buy Now |
DISTI #
220-1028-ND
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DigiKey | IC CPLD 256MC 5.8NS 144CSBGA Min Qty: 1800 Lead time: 20 Weeks Container: Tray | Temporarily Out of Stock |
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$24.5700 | Buy Now |
DISTI #
842-LC4256ZE-5MN144C
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Mouser Electronics | CPLD - Complex Programmable Logic Devices 256MC 108 I/O Lw Pwr 1.8V 5.8NS RoHS: Compliant | 0 |
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$24.5700 | Order Now |
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Future Electronics | 256MC 108 I/O Ultra Low Power 1.8V 5.8ns RoHS: Compliant pbFree: Yes Min Qty: 360 Package Multiple: 1800 Lead time: 20 Weeks | 0 |
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$25.2000 | Buy Now |
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LC4256ZE-5MN144C
Lattice Semiconductor Corporation
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Datasheet
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Compare Parts:
LC4256ZE-5MN144C
Lattice Semiconductor Corporation
EE PLD, 5.8ns, 256-Cell, CMOS, PBGA144, 7 X 7 MM, 0.5 MM PITCH, LEAD FREE, CSBGA-144
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Rohs Code | Yes | |
Part Life Cycle Code | Active | |
Ihs Manufacturer | LATTICE SEMICONDUCTOR CORP | |
Part Package Code | BGA | |
Package Description | 7 X 7 MM, 0.5 MM PITCH, LEAD FREE, CSBGA-144 | |
Pin Count | 144 | |
Reach Compliance Code | compliant | |
ECCN Code | EAR99 | |
HTS Code | 8542.39.00.01 | |
Samacsys Manufacturer | Lattice Semiconductor | |
Additional Feature | YES | |
Clock Frequency-Max | 149 MHz | |
In-System Programmable | YES | |
JESD-30 Code | S-PBGA-B144 | |
JESD-609 Code | e1 | |
JTAG BST | YES | |
Length | 7 mm | |
Moisture Sensitivity Level | 3 | |
Number of Dedicated Inputs | 4 | |
Number of I/O Lines | 108 | |
Number of Macro Cells | 256 | |
Number of Terminals | 144 | |
Organization | 4 DEDICATED INPUTS, 108 I/O | |
Output Function | MACROCELL | |
Package Body Material | PLASTIC/EPOXY | |
Package Code | TFBGA | |
Package Equivalence Code | BGA144,12X12,20 | |
Package Shape | SQUARE | |
Package Style | GRID ARRAY, THIN PROFILE, FINE PITCH | |
Peak Reflow Temperature (Cel) | 260 | |
Programmable Logic Type | EE PLD | |
Propagation Delay | 5.8 ns | |
Qualification Status | Not Qualified | |
Seated Height-Max | 1.1 mm | |
Supply Voltage-Max | 1.9 V | |
Supply Voltage-Min | 1.7 V | |
Supply Voltage-Nom | 1.8 V | |
Surface Mount | YES | |
Technology | CMOS | |
Terminal Finish | TIN SILVER COPPER | |
Terminal Form | BALL | |
Terminal Pitch | 0.5 mm | |
Terminal Position | BOTTOM | |
Time@Peak Reflow Temperature-Max (s) | 40 | |
Width | 7 mm |