Part Details for LM388 by National Semiconductor Corporation

Reference Design for the Stratix Vgx. This design takes into account sequencing needs. Applicable for 25W applications. 

This reference design showcases various power architectures for generating multiple voltage rails for an application processor module: requiring >1A load current and high efficiency . The required power supply is generated using 5-: 12- or 24-V DC input from the backplane. Power supplies are generated using DC-DC converters with an integrated FET and a power module with an integrated inductor for size. The design features a HotRod™ package type for applications requiring low EMI. It is also optimal for design time constrained applications. Additional features include DDR termination regulator: input supply OR-ing: voltage sequencing: eFuse for overload protection: and voltage and load current monitoring. This design can be used with a  processor: digital signal processor and field-programmable gate array. It has been tested for radiated emission: per CISPR22 meeting class A and B requirements.

The PMP4737 is a small synchronous boost with TPS61030 which supplies 4.2V@1.5A peak (GSM/GPRS module) from 2.5 to 3.6V source, which in this case is a supercap (super-capacitor).

PMP10711 is a 6-channel power supply sequencer that utilizes two LM3880 3-channel sequencer ICs. The design uses an external AND gate and OR gate to power up and power down all 6 channels in sequential fashion. This is useful in cases when up to 6 power rails need to be sequenced during power up and power down.

This small: efficient and flexible power supply for NXP™ IMX7 series application processors reference design was designed for iMX7 processors. This design uses five DC/DC converters and one sequencer IC to power the iMX7. It supports numerous industrial applications and any application that requires a small: high efficiency and flexible power supply.

This display reference design featuring TI's DLP2010 (.2 WVGA) DMD chipset, was designed to enable ultra low power and ultra mobile display applications either embedded inside a system (eg smartphone, tablets etc) or as a standalone accessory module. The chipset used in the design comprises of DL

The PMP10600.1 reference design provides all the power supply rails necessary to power Xilinx® Zynq® 7000 series (XC7Z015) FPGA.   This design uses several LMZ3 series modules: LDOs: and a DDR termination regulator.  It also features one LM3880 for power up and power down sequencing.  This design uses a 12V input.

The PMP9365 reference design provides all the power supply rails necessary to power Altera's Stratix V family of FPGAs.  This design uses several LMZ3 series modules: LDOs: and a DDR termination regulator to provide all the necessary rails to power the FPGA.  It also features two LM3880's for flexible power up and power down sequencing.  This design uses a 12V input.

The PMP9408 reference design provides all the power supply rails necessary to power the multi-gigabit transcievers (MGT) in Xilinx's Virtex® Ultrascale™ FPGAs.  It utilizes a PMBus interface for current and voltage monitoring and meets Xilinx's low output voltage ripple requirement.  This design uses a 5V input and offers a low cost discrete solution.

The PMP9353 reference design is a complete power solution for Altera Cyclone V SoC devices. This design uses several LMZ3 series modules : two LDOs: and a DDR termination regulator to provide all the necessary rails to power the SoC chip. This design also shows correct power-up sequencing.

The PMP9407 reference design provides all the power supply rails necessary to power the multi-gigabit transcievers (MGT) in Xilinx's Virtex® Ultrascale™ FPGAs.  This design uses a 5V input and has a PMBus interface for current and voltage monitoring: margining: timing delays: and fault monitoring.  It uses two TPS544B20's which feature internal current sensing and eliminate the need for an external current sense resistor.  This design also meets Xilinx's low output voltage ripple requirements of the MGT rails.

Electric meter developers often prefer to separate the energy measurement function from the host processor functions such as ANSI/IEC data tables, DLMS/COSEM, tariff management, and communications. This design demonstrates a method for keeping these meter functions separated by using an individua

This reference design demostrates a low cost single PCB board solution for 5V1A adapter. By using primary side regulation (PSR) mode chip UCC28720 which drives bipolar power device, average efficiency is 76%@115V and 77%@230Vac. PMP4373 achieves high precise CC and CV regulation with 0.15V cable compensation The overall size is limited in 35.7mm(L)* 25.7mm(W)*14mm(H) and no load power is less than 10mW. The design is done with single PCB layer.

This simple isolated flyback converts 30V…70Vin to 7V@430mA. The LM5021-2 controller is suitable for green mode converters due to pulse skip mode.

Power over Ethernet (PoE) enables power to be delivered over the same ethernet cable as data with no danger of cross-talk: interference: or corruption of the data streams. This reference design showcases end-to-end power tree for an IP network camera powered using PoE or 12-V adapter based on the TI’s DaVinci™ Digital Media Processor or different application processor. The power tree also derives rails required for different peripherals of an IP network camera like: Image sensor: motor control: Ethernet PHY: RS485 interface: IR LED illumination: audio: motion sensing and the alarm interface.

The PMP10630 reference design is a complete high density power solution for Xilinx® Kintex® UltraScale™ XCKU040 FPGA. This design uses an optimal combination of SIMPLE SWITCHER® modules and LDOs to provide all the necessary voltage rails in a small solution size of 36 x 43 mm (1.4 x 1.7 inch). The design includes the LMZ31704 LMZ3 series module to power the core rail and three LMZ21700/1 Nano series modules. The design manages the proper power sequencing using LM3880 sequencer: and it also has an optional DDR3 memory power supply featuring the LP2998 DDR termination regulator. The reference design takes 12V DC input voltage: and the total output power is 6W.

This reference design showcases a method to generate power supplies required in a servo or AC drive including the analog and digtal I/O interfaces: encoder supply: isolated transceivers and digital processing block. This design also implements protection against input reverse polarity: output overload and short circuit conditions.

The PMP10601 reference design provides all the power supply rails necessary to power Xilinx® Zynq® 7000 series (XC7Z015)  FPGA.   This design uses several LMZ3 series modules: LDOs: and a DDR termination regulator to provide all the necessary rails to power the FPGA.  It also features one LM3880 for  power up and power down sequencing.  This design uses a 12V input.

此汽车电源参考设计基于 LM25141-Q1 控制器，可通过 8.0V 至 16.0V 的输入电压提供 3.3V(6.0A)。

PMP10505 is a boost converter for LEDs which utilizes the LM5020-2 controller.  The switching frequency is set to 100 kHz for high efficiency at a nominal output power of 18.5W. The design features switch current limiting, output over-voltage limiting and summing feedback for multiple LED st

The PMP10555 reference design provides all the power supply rails necessary to power Xilinx® Ultrascale® 16nm family of FPGAs/SoCs in a mobile radio basestation application.   This design uses a PMBus compatible 20A integrated FET buck converter for the core and two multi-output buck regulator ICs to provide the remaining supplies necessary rails to power the FPGA.  It also features two LM3880's for flexible power up and power down sequencing.  This design uses a 12V input.

The PMP10520 reference design provides all the power supply rails (1V/20A: 1.2V/30A: 1.8V/4A) necessary to power the multi-gigabit transcievers (MGT) in Xilinx's Virtex® Ultrascale™  FPGAs.  This design uses a 5V input and has a PMBus interface for current and voltage monitoring: margining: timing delays: and fault monitoring.  It uses both TPS544C20 and TPS544B20 which feature internal current sensing and eliminate the need for an external current sense resistor.  This design also meets Xilinx's low output voltage ripple requirements of the MGT rails.

TIDA-01333 隔离式高电压模拟输入模块参考设计有八个通道，每个通道都支持电压和电流测量。此外，其中 4 个通道还支持高达 ±160V 的共模电压。该器件通过 ISOW7841 在单个芯片内实现了 +5V 线路和串行外设接口 (SPI) 通信的隔离。该设计采用了 ADS8681，这是一款 16 位模数转换器 (ADC)，可以处理高达 ±12.288V 的输入电压。因此无需再对工业领域中的标准输入电压进行任何预处理。

This design is a tiny synchronous buck converter which can be used either for 3.3V or 5.0V output voltage and a maximum current of 600mA. It has the same size like a TO-220 package and can directly replace linear regulators like the well-known uA7805.

PMP20634 参考设计是一种隔离式 DCM 反激设计，可提供 85V 到 265V 的通用交流线路输入，并产生一个能承受 12W 负载的 12V 输出。该设计使用 UCC28730 控制器，可在无负载的情况下实现超低待机功耗。它可在高压和低压线路中实现 85% 的效率，在 2 层电路板上的尺寸为 1 x 3 英寸。

The TIDA-00573 reference design provides a Class D based amplifier solution that allows it to be evaluated in the form factor of a typical Class AB amplifier.  The design is optimized to mitigate thermals associated with audio amplifiers and to minimize switching noises associated with Class

PMP8671 是基于汽车级质量控制器 IC (TPS40210-Q1) 的单端初级电感器转换器 (SEPIC) 参考设计。其输入电压范围为 4.5V 至 24V，提供 6.25V (1.2A) 的最大输出电流。开关频率设置为 400kHz，以提供出色的负载和线路调节，同时保持良好的相位和增益裕量。该参考设计专为汽车应用而设计，能够以低至 3V 的电压进行冷启动。

The PMP9463 reference design provides all the power supply rails necessary to power the multi-gigabit transcievers (MGT) in Xilinx's Ultrascale™ Kintex® FPGAs.  It utilizes a PMBus interface for current and voltage monitoring and meets Xilinx's low output voltage ripple requirement.  This design uses a 5V input and offers a low cost discrete solution.

The sole objective of this reference design is to provide comprehensive details on how to design a simple, robust, and accurate analog front end (AFE) circuit for making precision temperature measurements with thermocouple sensors. TIDA-00168 explains the theory, operation, and complications invo

PMP10652 is a System optimized (CISPR 25 Class 3) 30W design for Surround View ADAS system.The design has various protections such as Load dump through TVS (ISO pulse testing): Reverse Voltage (Innovative Smart diode with very low Iq): Battery Disconnect Switch with OVP protection (PFET) and is EMI optimized to meet Conductive EMI limits of CISPR25 Class3 (overall) and Class5 upto 30MHz Range.Input voltage range is between 4.5V to 30V with OVP at 20V and hence will operate in most Cold Cranking conditions.LM74610 is used for Battery reverse protection which utilizes a charge pump to drive an N-channel FET to provide a resistive path for the bypass current to flow. LM53603Q1 is used as front end DC/DC Buck converter which is 2.2MHz switching: Synchronous rectified Wide Vin Buck Converter which can take transient upto 42V. TPS57114Q1 is used to provide power to the cores and it is a high current 2:2MHz switching buck converter. LM26420 is a dual 2.2MHz switching buck converter which is used for generating other required supplies.LM3880 sequencer is used for all the power up and power down sequencing requirements.

Made in partnership with Avnet and Xilinx, the Spartan-6 LX150T Development Kit provides a complete development platform for the Spartan-6 LXT FPGA family. The Spartan-6 LX150T includes onboard serial gigabit transceiver interface interfaces (GTP) which, when used with the appropriate FPGA IP, enable support for PCI Express or SATA. The board also includes FMC expansion slots to extend the application specific functions.

The PMP10613 reference design provides all the power supply rails necessary to power Xilinx® Zynq® 7000 series (XC7Z045)  FPGA.   This design uses several LMZ3 series modules: LDOs: and a DDR termination regulator to provide all the necessary rails to power the FPGA.  It also features one LM3880 for  power up and power down sequencing.  This design uses a 12V input.