Part Details for SN74LVC112APWE4 by Texas Instruments
Overview of SN74LVC112APWE4 by Texas Instruments
- Distributor Offerings: (0 listings)
- Number of FFF Equivalents: (10 replacements)
- CAD Models: (Request Part)
- Number of Functional Equivalents: (10 options)
- Part Data Attributes: (Available)
- Reference Designs: (Not Available)
Tip: Data for a part may vary between manufacturers. You can filter for manufacturers on the top of the page next to the part image and part number.
Applications
Telecommunications
Part Details for SN74LVC112APWE4
SN74LVC112APWE4 CAD Models
SN74LVC112APWE4 Part Data Attributes
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SN74LVC112APWE4
Texas Instruments
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SN74LVC112APWE4
Texas Instruments
Dual Negative-Edge-Triggered J-K Flip-Flop With Clear And Preset 16-TSSOP -40 to 125
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| Rohs Code | Yes | |
| Part Life Cycle Code | Obsolete | |
| Ihs Manufacturer | TEXAS INSTRUMENTS INC | |
| Part Package Code | TSSOP | |
| Package Description | TSSOP, TSSOP16,.25 | |
| Pin Count | 16 | |
| Reach Compliance Code | compliant | |
| HTS Code | 8542.39.00.01 | |
| Family | LVC/LCX/Z | |
| JESD-30 Code | R-PDSO-G16 | |
| JESD-609 Code | e4 | |
| Length | 5 mm | |
| Load Capacitance (CL) | 50 pF | |
| Logic IC Type | J-K FLIP-FLOP | |
| Max Frequency@Nom-Sup | 150000000 Hz | |
| Max I(ol) | 0.024 A | |
| Moisture Sensitivity Level | 1 | |
| Number of Bits | 2 | |
| Number of Functions | 2 | |
| Number of Terminals | 16 | |
| Operating Temperature-Max | 125 °C | |
| Operating Temperature-Min | -40 °C | |
| Output Polarity | COMPLEMENTARY | |
| Package Body Material | PLASTIC/EPOXY | |
| Package Code | TSSOP | |
| Package Equivalence Code | TSSOP16,.25 | |
| Package Shape | RECTANGULAR | |
| Package Style | SMALL OUTLINE, THIN PROFILE, SHRINK PITCH | |
| Packing Method | TUBE | |
| Peak Reflow Temperature (Cel) | 260 | |
| Prop. Delay@Nom-Sup | 5.9 ns | |
| Propagation Delay (tpd) | 7.1 ns | |
| Qualification Status | Not Qualified | |
| Seated Height-Max | 1.2 mm | |
| Supply Voltage-Max (Vsup) | 3.6 V | |
| Supply Voltage-Min (Vsup) | 1.65 V | |
| Supply Voltage-Nom (Vsup) | 1.8 V | |
| Surface Mount | YES | |
| Technology | CMOS | |
| Temperature Grade | AUTOMOTIVE | |
| Terminal Finish | NICKEL PALLADIUM GOLD | |
| Terminal Form | GULL WING | |
| Terminal Pitch | 0.65 mm | |
| Terminal Position | DUAL | |
| Time@Peak Reflow Temperature-Max (s) | 30 | |
| Trigger Type | NEGATIVE EDGE | |
| Width | 4.4 mm | |
| fmax-Min | 150 MHz |
Alternate Parts for SN74LVC112APWE4
This table gives cross-reference parts and alternative options found for SN74LVC112APWE4. The Form Fit Function (FFF) tab will give you the options that are more likely to serve as direct pin-to-pin alternates or drop-in parts. The Functional Equivalents tab will give you options that are likely to match the same function of SN74LVC112APWE4, but it may not fit your design. Always verify details of parts you are evaluating, as these parts are offered as suggestions for what you are looking for and are not guaranteed.
| Part Number | Description | Manufacturer | Compare |
|---|---|---|---|
| 74LCX112MTCX | Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant Inputs, 2500-REEL | onsemi | SN74LVC112APWE4 vs 74LCX112MTCX |
| 74LCX112MTC | J-K Flip-Flop, LVC/LCX/Z Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO16, 4.40 MM, MO-153, TSSOP-16 | Fairchild Semiconductor Corporation | SN74LVC112APWE4 vs 74LCX112MTC |
| SN74LVC112APWTE4 | LVC/LCX/Z SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, GREEN, PLASTIC, TSSOP-16 | Texas Instruments | SN74LVC112APWE4 vs SN74LVC112APWTE4 |
| 74LCX112MTCX_NL | J-K Flip-Flop, LVC/LCX/Z Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO16, 4.40 MM, MO-153, TSSOP-16 | Fairchild Semiconductor Corporation | SN74LVC112APWE4 vs 74LCX112MTCX_NL |
| SN74LVC112APWTG4 | Dual Negative-Edge-Triggered J-K Flip-Flop With Clear And Preset 16-TSSOP -40 to 85 | Texas Instruments | SN74LVC112APWE4 vs SN74LVC112APWTG4 |
| 74LCX112MTC | Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant Inputs, 2350-TUBE | onsemi | SN74LVC112APWE4 vs 74LCX112MTC |
| SN74LVC112APWT | Dual Negative-Edge-Triggered J-K Flip-Flop With Clear And Preset 16-TSSOP -40 to 125 | Texas Instruments | SN74LVC112APWE4 vs SN74LVC112APWT |
| IDT74LVC112APGG | J-K Flip-Flop, LVC/LCX/Z Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO16, TSSOP-16 | Integrated Device Technology Inc | SN74LVC112APWE4 vs IDT74LVC112APGG |
| IDT74LVC112APGG8 | J-K Flip-Flop, LVC/LCX/Z Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO16, TSSOP-16 | Integrated Device Technology Inc | SN74LVC112APWE4 vs IDT74LVC112APGG8 |
| IDT74LVC112AP | J-K Flip-Flop, LVC/LCX/Z Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO16, TSSOP-16 | Integrated Device Technology Inc | SN74LVC112APWE4 vs IDT74LVC112AP |