Part Details for XCVU9P-L2FLGA2104E by AMD Xilinx
Overview of XCVU9P-L2FLGA2104E by AMD Xilinx
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- Number of Functional Equivalents:
- Part Data Attributes
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Applications
Computing and Data Storage
Telecommunications
Price & Stock for XCVU9P-L2FLGA2104E
| Part # | Distributor | Description | Stock | Price | Buy | |
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DISTI #
17AH9534
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Newark | Fpga, Virtex Ultrascale+, Fcbga-2104, No. Of Logic Blocks:1182240, No. Of Macrocells:2586150, Fpga Family:Virtex Ultrascale+, Logic Case Style:Fcbga, No. Of Pins:2104Pins, No. Of Speed Grades:-, Total Ram Bits:77721.6Kbit, No. Of Rohs Compliant: Yes |Amd Xilinx XCVU9P-L2FLGA2104E Min Qty: 1 Package Multiple: 1 Date Code: 1 Container: Bulk | 0 |
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$61,158.5500 | Buy Now |
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DISTI #
3132157
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element14 Asia-Pacific | FPGA, VIRTEX ULTRASCALE+, FCBGA-2104 RoHS: Compliant Min Qty: 1 Container: Each | 0 |
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$63,241.4402 | Buy Now |
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DISTI #
3132157
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Farnell | FPGA, VIRTEX ULTRASCALE+, FCBGA-2104 RoHS: Compliant Min Qty: 1 Lead time: 21 Weeks, 1 Days Container: Each | 0 |
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$64,058.3744 | Buy Now |
Part Details for XCVU9P-L2FLGA2104E
XCVU9P-L2FLGA2104E CAD Models
XCVU9P-L2FLGA2104E Part Data Attributes
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XCVU9P-L2FLGA2104E
AMD Xilinx
Buy Now
Datasheet
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Compare Parts:
XCVU9P-L2FLGA2104E
AMD Xilinx
Field Programmable Gate Array
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| Rohs Code | Yes | |
| Part Life Cycle Code | Transferred | |
| Ihs Manufacturer | XILINX INC | |
| Reach Compliance Code | not_compliant | |
| ECCN Code | 3A001.A.7.B | |
| HTS Code | 8542.39.00.01 | |
| Date Of Intro | 2016-06-03 | |
| Additional Feature | ALSO OPERATES AT 0.85V NOMINAL SUPPLY | |
| JESD-30 Code | S-PBGA-B2104 | |
| Length | 47.5 mm | |
| Number of CLBs | 147780 | |
| Number of Inputs | 832 | |
| Number of Logic Cells | 2586150 | |
| Number of Outputs | 832 | |
| Number of Terminals | 2104 | |
| Operating Temperature-Max | 110 °C | |
| Operating Temperature-Min | ||
| Organization | 147780 CLBS | |
| Package Body Material | PLASTIC/EPOXY | |
| Package Code | BGA | |
| Package Equivalence Code | BGA2104,46X46,40 | |
| Package Shape | SQUARE | |
| Package Style | GRID ARRAY | |
| Packing Method | BOX; TRAY | |
| Peak Reflow Temperature (Cel) | NOT SPECIFIED | |
| Programmable Logic Type | FIELD PROGRAMMABLE GATE ARRAY | |
| Seated Height-Max | 4.24 mm | |
| Supply Voltage-Max | 0.742 V | |
| Supply Voltage-Min | 0.698 V | |
| Supply Voltage-Nom | 0.72 V | |
| Surface Mount | YES | |
| Terminal Form | BALL | |
| Terminal Pitch | 1 mm | |
| Terminal Position | BOTTOM | |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED | |
| Width | 47.5 mm |