5962-8947601LA vs 5962-8947601LA feature comparison

5962-8947601LA Altera Corporation

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5962-8947601LA Intel Corporation

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Part Life Cycle Code Obsolete Obsolete
Ihs Manufacturer ALTERA CORP INTEL CORP
Part Package Code DIP DIP
Package Description WDIP, WDIP,
Pin Count 24 24
Reach Compliance Code unknown unknown
ECCN Code 3A001.A.2.C 3A001.A.2.C
HTS Code 8542.39.00.01 8542.39.00.01
Additional Feature MACROCELLS INTERCONNECTED BY GLOBAL BUS; 16 MACROCELLS; 2 EXTERNAL CLOCKS MACROCELLS INTERCONNECTED BY GLOBAL BUS; 16 MACROCELLS; 2 EXTERNAL CLOCKS
Clock Frequency-Max 28.5 MHz 28.5 MHz
JESD-30 Code R-GDIP-T24 R-GDIP-T24
JESD-609 Code e0 e0
Length 32 mm 32 mm
Number of Dedicated Inputs 4 4
Number of I/O Lines 16 16
Number of Terminals 24 24
Operating Temperature-Max 125 °C 125 °C
Operating Temperature-Min -55 °C -55 °C
Organization 4 DEDICATED INPUTS, 16 I/O 4 DEDICATED INPUTS, 16 I/O
Output Function MACROCELL MACROCELL
Package Body Material CERAMIC, GLASS-SEALED CERAMIC, GLASS-SEALED
Package Code WDIP WDIP
Package Shape RECTANGULAR RECTANGULAR
Package Style IN-LINE, WINDOW IN-LINE, WINDOW
Programmable Logic Type UV PLD UV PLD
Propagation Delay 37 ns 37 ns
Qualification Status Not Qualified Not Qualified
Seated Height-Max 5.08 mm 5.08 mm
Supply Voltage-Max 5.5 V 5.5 V
Supply Voltage-Min 4.5 V 4.5 V
Supply Voltage-Nom 5 V 5 V
Surface Mount NO NO
Technology CMOS CMOS
Temperature Grade MILITARY MILITARY
Terminal Finish TIN LEAD TIN LEAD
Terminal Form THROUGH-HOLE THROUGH-HOLE
Terminal Pitch 2.54 mm 2.54 mm
Terminal Position DUAL DUAL
Width 7.62 mm 7.62 mm
Base Number Matches 1 1

Compare 5962-8947601LA with alternatives

Compare 5962-8947601LA with alternatives