D83C154DXXX vs QD80C51BH-2 feature comparison

D83C154DXXX Matra MHS

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QD80C51BH-2 Intel Corporation

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Part Life Cycle Code Obsolete Obsolete
Ihs Manufacturer MATRA MHS INTEL CORP
Reach Compliance Code unknown compliant
HTS Code 8542.31.00.01 8542.31.00.01
Has ADC NO NO
Additional Feature BOOLEAN PROCESSOR BOOLEAN PROCESSOR; EMULATION HARDWARE
Address Bus Width 16 16
Bit Size 8 8
Boundary Scan NO NO
Clock Frequency-Max 12 MHz 12 MHz
DAC Channels NO NO
DMA Channels NO NO
External Data Bus Width 8 8
Format FIXED POINT FIXED POINT
Integrated Cache NO NO
JESD-30 Code R-GDIP-T40 R-GDIP-T40
Low Power Mode YES YES
Number of DMA Channels
Number of External Interrupts 2 2
Number of I/O Lines 32 32
Number of Serial I/Os 1 1
Number of Terminals 40 40
Number of Timers 3 2
On Chip Data RAM Width 8 8
On Chip Program ROM Width 8 8
Operating Temperature-Max 70 °C 70 °C
Operating Temperature-Min
PWM Channels NO NO
Package Body Material CERAMIC, GLASS-SEALED CERAMIC, GLASS-SEALED
Package Shape RECTANGULAR RECTANGULAR
Package Style IN-LINE IN-LINE
Qualification Status Not Qualified Not Qualified
RAM (words) 256 128
ROM (words) 32768 4096
ROM Programmability MROM UVPROM
Speed 12 MHz 12 MHz
Supply Current-Max 32 mA 20 mA
Supply Voltage-Max 5.5 V 6 V
Supply Voltage-Min 5 V 5 V
Supply Voltage-Nom 5 V 5 V
Surface Mount NO NO
Technology CMOS CMOS
Temperature Grade COMMERCIAL COMMERCIAL
Terminal Form THROUGH-HOLE THROUGH-HOLE
Terminal Position DUAL DUAL
uPs/uCs/Peripheral ICs Type MICROCONTROLLER MICROCONTROLLER
Base Number Matches 1 1
Rohs Code No
Part Package Code DIP
Package Description CERDIP-40
Pin Count 40
CPU Family 8051
JESD-609 Code e0
Length 52.325 mm
Package Code DIP
Package Equivalence Code DIP40,.6
RAM (bytes) 128
Seated Height-Max 5.72 mm
Terminal Finish TIN LEAD
Terminal Pitch 2.54 mm
Width 15.24 mm

Compare D83C154DXXX with alternatives

Compare QD80C51BH-2 with alternatives