FDG312P_NL
vs
SI1407DL-T1-E3
feature comparison
| Rohs Code |
Yes
|
Yes
|
| Part Life Cycle Code |
Obsolete
|
Obsolete
|
| Ihs Manufacturer |
FAIRCHILD SEMICONDUCTOR CORP
|
VISHAY INTERTECHNOLOGY INC
|
| Part Package Code |
SC-70
|
|
| Package Description |
SMALL OUTLINE, R-PDSO-G6
|
ROHS COMPLIANT, SC-70, 6 PIN
|
| Pin Count |
6
|
|
| Reach Compliance Code |
compliant
|
compliant
|
| ECCN Code |
EAR99
|
EAR99
|
| Configuration |
SINGLE WITH BUILT-IN DIODE
|
SINGLE WITH BUILT-IN DIODE
|
| DS Breakdown Voltage-Min |
20 V
|
12 V
|
| Drain Current-Max (ID) |
1.2 A
|
1.6 A
|
| Drain-source On Resistance-Max |
0.18 Ω
|
0.13 Ω
|
| FET Technology |
METAL-OXIDE SEMICONDUCTOR
|
METAL-OXIDE SEMICONDUCTOR
|
| JESD-30 Code |
R-PDSO-G6
|
R-PDSO-G6
|
| JESD-609 Code |
e3
|
e3
|
| Moisture Sensitivity Level |
1
|
1
|
| Number of Elements |
1
|
1
|
| Number of Terminals |
6
|
6
|
| Operating Mode |
ENHANCEMENT MODE
|
ENHANCEMENT MODE
|
| Operating Temperature-Max |
150 °C
|
150 °C
|
| Operating Temperature-Min |
-55 °C
|
|
| Package Body Material |
PLASTIC/EPOXY
|
PLASTIC/EPOXY
|
| Package Shape |
RECTANGULAR
|
RECTANGULAR
|
| Package Style |
SMALL OUTLINE
|
SMALL OUTLINE
|
| Peak Reflow Temperature (Cel) |
260
|
|
| Polarity/Channel Type |
P-CHANNEL
|
P-CHANNEL
|
| Power Dissipation-Max (Abs) |
0.75 W
|
0.625 W
|
| Qualification Status |
Not Qualified
|
Not Qualified
|
| Surface Mount |
YES
|
YES
|
| Terminal Finish |
MATTE TIN
|
MATTE TIN
|
| Terminal Form |
GULL WING
|
GULL WING
|
| Terminal Position |
DUAL
|
DUAL
|
| Time@Peak Reflow Temperature-Max (s) |
40
|
|
| Transistor Application |
SWITCHING
|
|
| Transistor Element Material |
SILICON
|
SILICON
|
| Base Number Matches |
1
|
1
|
|
|
|
Compare FDG312P_NL with alternatives
Compare SI1407DL-T1-E3 with alternatives