J113 vs J112 feature comparison

J113 Allegro MicroSystems LLC

Buy Now Datasheet

J112 Linear Integrated Systems

Buy Now Datasheet
Rohs Code No Yes
Part Life Cycle Code Obsolete Active
Ihs Manufacturer ALLEGRO MICROSYSTEMS LLC LINEAR INTEGRATED SYSTEMS INC
Reach Compliance Code unknown compliant
ECCN Code EAR99 EAR99
Configuration SINGLE SINGLE
Drain-source On Resistance-Max 100 Ω 50 Ω
FET Technology JUNCTION JUNCTION
Feedback Cap-Max (Crss) 5 pF 5 pF
JEDEC-95 Code TO-226AA TO-92
JESD-30 Code O-PBCY-T3 O-PBCY-T3
JESD-609 Code e0 e3
Number of Elements 1 1
Number of Terminals 3 3
Operating Mode DEPLETION MODE DEPLETION MODE
Operating Temperature-Max 150 °C 135 °C
Package Body Material PLASTIC/EPOXY PLASTIC/EPOXY
Package Shape ROUND ROUND
Package Style CYLINDRICAL CYLINDRICAL
Polarity/Channel Type N-CHANNEL N-CHANNEL
Power Dissipation-Max (Abs) 0.4 W
Qualification Status Not Qualified Not Qualified
Surface Mount NO NO
Terminal Finish TIN LEAD MATTE TIN
Terminal Form THROUGH-HOLE THROUGH-HOLE
Terminal Position BOTTOM BOTTOM
Transistor Element Material SILICON SILICON
Base Number Matches 50 5
Pbfree Code Yes
Part Package Code TO-92
Pin Count 3
Moisture Sensitivity Level 1
Transistor Application SWITCHING

Compare J113 with alternatives

Compare J112 with alternatives