J113_D74Z vs J112 feature comparison

J113_D74Z Fairchild Semiconductor Corporation

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J112 Linear Integrated Systems

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Pbfree Code Yes Yes
Rohs Code Yes Yes
Part Life Cycle Code Transferred Active
Ihs Manufacturer FAIRCHILD SEMICONDUCTOR CORP LINEAR INTEGRATED SYSTEMS INC
Part Package Code TO-92 TO-92
Package Description CYLINDRICAL, O-PBCY-T3
Pin Count 3 3
Manufacturer Package Code 3LD, TO-92, MOLDED, 0.200 IN LINE SPACING LD FORM (J61Z OPTION)
Reach Compliance Code compliant compliant
ECCN Code EAR99 EAR99
HTS Code 8541.21.00.95
Configuration SINGLE SINGLE
Drain-source On Resistance-Max 100 Ω 50 Ω
FET Technology JUNCTION JUNCTION
Feedback Cap-Max (Crss) 5 pF 5 pF
JEDEC-95 Code TO-92 TO-92
JESD-30 Code O-PBCY-T3 O-PBCY-T3
JESD-609 Code e1 e3
Number of Elements 1 1
Number of Terminals 3 3
Operating Mode DEPLETION MODE DEPLETION MODE
Operating Temperature-Max 150 °C 135 °C
Package Body Material PLASTIC/EPOXY PLASTIC/EPOXY
Package Shape ROUND ROUND
Package Style CYLINDRICAL CYLINDRICAL
Polarity/Channel Type N-CHANNEL N-CHANNEL
Power Dissipation-Max (Abs) 0.4 W
Qualification Status Not Qualified Not Qualified
Surface Mount NO NO
Terminal Finish TIN SILVER COPPER MATTE TIN
Terminal Form THROUGH-HOLE THROUGH-HOLE
Terminal Position BOTTOM BOTTOM
Transistor Application SWITCHING SWITCHING
Transistor Element Material SILICON SILICON
Base Number Matches 2 28
Moisture Sensitivity Level 1

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