PDTA115EEF vs PDTA115ES feature comparison

PDTA115EEF Nexperia

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PDTA115ES NXP Semiconductors

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Part Life Cycle Code Active Transferred
Ihs Manufacturer NEXPERIA NXP SEMICONDUCTORS
Package Description SMALL OUTLINE, R-PDSO-F3 PLASTIC, SC-43A, 3 PIN
Reach Compliance Code compliant unknown
ECCN Code EAR99 EAR99
Date Of Intro 2017-02-01
Additional Feature BUILT-IN BIAS RESISTOR RATIO IS 1 BUILT-IN BIAS RESISTOR RATIO IS 1
Collector Current-Max (IC) 0.02 A 0.02 A
Collector-Emitter Voltage-Max 50 V 50 V
Configuration SINGLE WITH BUILT-IN RESISTOR SINGLE WITH BUILT-IN RESISTOR
DC Current Gain-Min (hFE) 80 80
JESD-30 Code R-PDSO-F3 O-PBCY-T3
Number of Elements 1 1
Number of Terminals 3 3
Package Body Material PLASTIC/EPOXY PLASTIC/EPOXY
Package Shape RECTANGULAR ROUND
Package Style SMALL OUTLINE CYLINDRICAL
Polarity/Channel Type PNP PNP
Surface Mount YES NO
Terminal Form FLAT THROUGH-HOLE
Terminal Position DUAL BOTTOM
Transistor Application SWITCHING SWITCHING
Transistor Element Material SILICON SILICON
Base Number Matches 3 3
Rohs Code Yes
Part Package Code TO-92
Pin Count 3
JEDEC-95 Code TO-92
JESD-609 Code e3
Moisture Sensitivity Level 1
Power Dissipation-Max (Abs) 0.5 W
Qualification Status Not Qualified
Terminal Finish Matte Tin (Sn)

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