PDTA115EU
vs
PDTA115EEF
feature comparison
| Rohs Code |
Yes
|
|
| Part Life Cycle Code |
Active
|
Transferred
|
| Ihs Manufacturer |
NEXPERIA
|
NXP SEMICONDUCTORS
|
| Package Description |
PLASTIC, SC-70, 3 PIN
|
SMALL OUTLINE, R-PDSO-F3
|
| Reach Compliance Code |
compliant
|
unknown
|
| ECCN Code |
EAR99
|
EAR99
|
| Date Of Intro |
2017-02-01
|
|
| Samacsys Manufacturer |
Nexperia
|
|
| Additional Feature |
BUILT-IN BIAS RESISTOR RATIO IS 1
|
BUILT-IN BIAS RESISTOR RATIO IS 1
|
| Collector Current-Max (IC) |
0.02 A
|
0.02 A
|
| Collector-Emitter Voltage-Max |
50 V
|
50 V
|
| Configuration |
SINGLE WITH BUILT-IN RESISTOR
|
SINGLE WITH BUILT-IN RESISTOR
|
| DC Current Gain-Min (hFE) |
80
|
80
|
| JESD-30 Code |
R-PDSO-G3
|
R-PDSO-F3
|
| JESD-609 Code |
e3
|
|
| Moisture Sensitivity Level |
1
|
|
| Number of Elements |
1
|
1
|
| Number of Terminals |
3
|
3
|
| Package Body Material |
PLASTIC/EPOXY
|
PLASTIC/EPOXY
|
| Package Shape |
RECTANGULAR
|
RECTANGULAR
|
| Package Style |
SMALL OUTLINE
|
SMALL OUTLINE
|
| Peak Reflow Temperature (Cel) |
260
|
|
| Polarity/Channel Type |
PNP
|
PNP
|
| Reference Standard |
AEC-Q101
|
|
| Surface Mount |
YES
|
YES
|
| Terminal Finish |
TIN
|
|
| Terminal Form |
GULL WING
|
FLAT
|
| Terminal Position |
DUAL
|
DUAL
|
| Time@Peak Reflow Temperature-Max (s) |
30
|
|
| Transistor Application |
SWITCHING
|
SWITCHING
|
| Transistor Element Material |
SILICON
|
SILICON
|
| Base Number Matches |
2
|
2
|
| Part Package Code |
|
SC-89
|
| Pin Count |
|
3
|
| Power Dissipation-Max (Abs) |
|
0.25 W
|
| Qualification Status |
|
Not Qualified
|
|
|
|
Compare PDTA115EU with alternatives
Compare PDTA115EEF with alternatives