Parametric results for: 5962-8994801YC under Field Programmable Gate Arrays

All Filters Clock Frequency-Max Combinatorial Delay of a CLB-Max JESD-30 Code JESD-609 Code Length Manufacturer Number of CLBs Number of Equivalent Gates Number of Terminals Operating Temperature-Max Operating Temperature-Min Organization Package Body Material Package Code Package Shape Package Style Part Life Cycle Code Programmable Logic Type Qualification Status Screening Level Seated Height-Max Supply Voltage-Max Supply Voltage-Min Supply Voltage-Nom Surface Mount Technology Temperature Grade Terminal Finish Terminal Form

16 MHz 1

1 hit Apply

Combinatorial Delay of a CLB-Max (1)

14 ns 1

1 hit Apply

S-XQFP-F100 1

1 hit Apply

e4 1

1 hit Apply

17.27 mm 1

1 hit Apply

Manufacturer (1)

AMD Xilinx 1

1 hit Apply

Number of CLBs (1)

64 1

1 hit Apply

Number of Equivalent Gates (1)

2000 1

1 hit Apply

100 1

1 hit Apply

125.0 °C 1

1 hit Apply

-55.0 °C 1

1 hit Apply

64 CLBS, 2000 GATES 1

1 hit Apply

UNSPECIFIED 1

1 hit Apply

QFF 1

1 hit Apply

Package Shape (1)

SQUARE 1

1 hit Apply

FLATPACK 1

1 hit Apply

Obsolete 1

1 hit Apply

Programmable Logic Type (1)

FIELD PROGRAMMABLE GATE ARRAY 1

1 hit Apply

Not Qualified 1

1 hit Apply

Screening Level (1)

MIL-STD-883 1

1 hit Apply

3.68 mm 1

1 hit Apply

5.5 V 1

1 hit Apply

4.5 V 1

1 hit Apply

Supply Voltage-Nom (1)

5 V 1

1 hit Apply

YES 1

1 hit Apply

CMOS 1

1 hit Apply

Temperature Grade (1)

MILITARY 1

1 hit Apply

GOLD 1

1 hit Apply

FLAT 1

1 hit Apply