Parametric results for: CD4572UBNSR under Gates

All Filters Additional Feature Family JESD-30 Code JESD-609 Code Length Load Capacitance (CL) Logic IC Type Manufacturer Max I(ol) Moisture Sensitivity Level Number of Functions Number of Inputs Number of Terminals Operating Temperature-Max Operating Temperature-Min Package Body Material Package Code Package Equivalence Code Package Shape Package Style Prop. Delay@Nom-Sup Propagation Delay (tpd) Schmitt Trigger Supply Voltage-Nom (Vsup) Surface Mount

MIXED WITH ONE 2-INPUT NOR & ONE 2-INPUT NAND GATE 3

3 hits Apply

Family (1)

4000/14000/40000 3

3 hits Apply

R-PDSO-G16 3

3 hits Apply

e4 3

3 hits Apply

10.2 mm 3

3 hits Apply

Load Capacitance (CL) (1)

50 pF 3

3 hits Apply

INVERTER 3

3 hits Apply

Manufacturer (1)

Texas Instruments 3

3 hits Apply

6.8 mA 1

3 hits Apply

1 3

3 hits Apply

Number of Functions (2)

4.0 2 6.0 1

Min - Max

3 hits Apply

Number of Inputs (1)

1 3

3 hits Apply

16 3

3 hits Apply

125.0 °C 3

3 hits Apply

-55.0 °C 3

3 hits Apply

PLASTIC/EPOXY 3

3 hits Apply

Package Code (1)

SOP 3

3 hits Apply

SOP16,.3 3

3 hits Apply

RECTANGULAR 3

3 hits Apply

SMALL OUTLINE 3

3 hits Apply

Prop. Delay@Nom-Sup (1)

200 ns 3

3 hits Apply

Propagation Delay (tpd) (1)

200 ns 3

3 hits Apply

Schmitt Trigger (1)

NO 3

3 hits Apply

Supply Voltage-Nom (Vsup) (1)

5 V 3

3 hits Apply

Surface Mount (1)

YES 3

3 hits Apply