Parametric results for: ICE40LP640-SWG16TR under Field Programmable Gate Arrays

All Filters Combinatorial Delay of a CLB-Max JESD-30 Code Length Manufacturer Number of CLBs Number of Inputs Number of Logic Cells Number of Outputs Number of Terminals Operating Temperature-Max Operating Temperature-Min Organization Package Body Material Package Code Package Shape Package Style Part Life Cycle Code Peak Reflow Temperature (Cel) Programmable Logic Type Rohs Code Seated Height-Max Supply Voltage-Max Supply Voltage-Min Supply Voltage-Nom Surface Mount Technology Temperature Grade Terminal Form Combinatorial Delay of a CLB-Max (1)

9.36 ns 2

3 hits Apply

R-PBGA-B16 3

3 hits Apply

1.48 mm 3

3 hits Apply

Manufacturer (1)

Lattice Semiconductor Corporation 3

3 hits Apply

Number of CLBs (1)

80 3

3 hits Apply

Number of Inputs (1)

10 2

3 hits Apply

Number of Logic Cells (1)

640 2

3 hits Apply

Number of Outputs (1)

10 2

3 hits Apply

16 3

3 hits Apply

100.0 °C 3

3 hits Apply

-40.0 °C 3

3 hits Apply

80 CLBS 3

3 hits Apply

PLASTIC/EPOXY 3

3 hits Apply

VFBGA 3

3 hits Apply

Package Shape (1)

RECTANGULAR 3

3 hits Apply

GRID ARRAY, VERY THIN PROFILE, FINE PITCH 3

3 hits Apply

Active 2 Obsolete 1

3 hits Apply

NOT SPECIFIED 3

3 hits Apply

Programmable Logic Type (1)

FIELD PROGRAMMABLE GATE ARRAY 3

3 hits Apply

Yes 3

3 hits Apply

491 µm 3

3 hits Apply

1.26 V 3

3 hits Apply

1.14 V 3

3 hits Apply

Supply Voltage-Nom (1)

1.2 V 3

3 hits Apply

YES 3

3 hits Apply

CMOS 3

3 hits Apply

Temperature Grade (1)

INDUSTRIAL 3

3 hits Apply

BALL 3

3 hits Apply