Parametric results for: ICE5LP2K-SWG36ITR under Field Programmable Gate Arrays

All Filters Combinatorial Delay of a CLB-Max JESD-30 Code Length Manufacturer Moisture Sensitivity Level Number of CLBs Number of Inputs Number of Logic Cells Number of Outputs Number of Terminals Operating Temperature-Max Operating Temperature-Min Organization Package Body Material Package Code Package Equivalence Code Package Shape Package Style Packing Method Part Life Cycle Code Peak Reflow Temperature (Cel) Programmable Logic Type Rohs Code Seated Height-Max Supply Voltage-Max Supply Voltage-Min Supply Voltage-Nom Surface Mount Technology Terminal Form Combinatorial Delay of a CLB-Max (1)

9 ns 2

3 hits Apply

S-PBGA-B36 2

3 hits Apply

2.078 mm 2

3 hits Apply

Manufacturer (1)

Lattice Semiconductor Corporation 3

3 hits Apply

1 3

3 hits Apply

Number of CLBs (1)

256 2

3 hits Apply

Number of Inputs (1)

26 2

3 hits Apply

Number of Logic Cells (1)

2048 2

3 hits Apply

Number of Outputs (1)

26 2

3 hits Apply

36 2

3 hits Apply

100.0 °C 2

3 hits Apply

-40.0 °C 2

3 hits Apply

256 CLBS 2

3 hits Apply

PLASTIC/EPOXY 2

3 hits Apply

VFBGA 2

3 hits Apply

BGA36,6X6,14 2

3 hits Apply

Package Shape (1)

SQUARE 2

3 hits Apply

GRID ARRAY, VERY THIN PROFILE, FINE PITCH 2

3 hits Apply

TR 2

3 hits Apply

Active 2 Obsolete 1

3 hits Apply

260 3

3 hits Apply

Programmable Logic Type (1)

FIELD PROGRAMMABLE GATE ARRAY 3

3 hits Apply

Yes 2

3 hits Apply

491 µm 2

3 hits Apply

1.26 V 2

3 hits Apply

1.14 V 2

3 hits Apply

Supply Voltage-Nom (1)

1.2 V 2

3 hits Apply

YES 2

3 hits Apply

CMOS 2

3 hits Apply

BALL 2

3 hits Apply