Parametric results for: SN74LV11ATPWREP under Gates

All Filters Family JESD-30 Code JESD-609 Code Length Load Capacitance (CL) Logic IC Type Manufacturer Max I(ol) Moisture Sensitivity Level Number of Functions Number of Inputs Number of Terminals Operating Temperature-Max Operating Temperature-Min Package Body Material Package Code Package Equivalence Code Package Shape Package Style Prop. Delay@Nom-Sup Propagation Delay (tpd) Schmitt Trigger Supply Voltage-Nom (Vsup) Surface Mount Family (1)

LV/LV-A/LVX/H 1

1 hit Apply

R-PDSO-G14 1

1 hit Apply

e4 1

1 hit Apply

5 mm 1

1 hit Apply

Load Capacitance (CL) (1)

50 pF 1

1 hit Apply

AND GATE 1

1 hit Apply

Manufacturer (1)

Texas Instruments 1

1 hit Apply

12 mA 1

1 hit Apply

1 1

1 hit Apply

Number of Functions (1)

3.0 1

1 hit Apply

Number of Inputs (1)

3 1

1 hit Apply

14 1

1 hit Apply

105.0 °C 1

1 hit Apply

-40.0 °C 1

1 hit Apply

PLASTIC/EPOXY 1

1 hit Apply

Package Code (1)

TSSOP 1

1 hit Apply

TSSOP14,.25 1

1 hit Apply

RECTANGULAR 1

1 hit Apply

SMALL OUTLINE, THIN PROFILE, SHRINK PITCH 1

1 hit Apply

Prop. Delay@Nom-Sup (1)

14 ns 1

1 hit Apply

Propagation Delay (tpd) (1)

21 ns 1

1 hit Apply

Schmitt Trigger (1)

NO 1

1 hit Apply

Supply Voltage-Nom (Vsup) (1)

2.5 V 1

1 hit Apply

Surface Mount (1)

YES 1

1 hit Apply