Parametric results for: XC4010E-2PG191C under Field Programmable Gate Arrays

All Filters Additional Feature Clock Frequency-Max Combinatorial Delay of a CLB-Max JESD-30 Code Length Manufacturer Number of CLBs Number of Equivalent Gates Number of Inputs Number of Logic Cells Number of Outputs Number of Terminals Operating Temperature-Max Operating Temperature-Min Organization Package Body Material Package Code Package Equivalence Code Package Shape Package Style Part Life Cycle Code Programmable Logic Type Qualification Status Rohs Code Seated Height-Max Supply Voltage-Max Supply Voltage-Min Supply Voltage-Nom Surface Mount Technology Temperature Grade Terminal Form

MAX USABLE 10000 LOGIC GATES 1

1 hit Apply

125 MHz 1

1 hit Apply

Combinatorial Delay of a CLB-Max (1)

1.6 ns 1

1 hit Apply

S-CPGA-P191 1

1 hit Apply

47.244 mm 1

1 hit Apply

Manufacturer (1)

AMD Xilinx 1

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Number of CLBs (1)

400 1

1 hit Apply

Number of Equivalent Gates (1)

7000 1

1 hit Apply

Number of Inputs (1)

160 1

1 hit Apply

Number of Logic Cells (1)

400 1

1 hit Apply

Number of Outputs (1)

160 1

1 hit Apply

191 1

1 hit Apply

85.0 °C 1

1 hit Apply

0.0 °C 1

1 hit Apply

400 CLBS, 7000 GATES 1

1 hit Apply

CERAMIC, METAL-SEALED COFIRED 1

1 hit Apply

HPGA 1

1 hit Apply

PGA191M,18X18 1

1 hit Apply

Package Shape (1)

SQUARE 1

1 hit Apply

GRID ARRAY, HEAT SINK/SLUG 1

1 hit Apply

Obsolete 1

1 hit Apply

Programmable Logic Type (1)

FIELD PROGRAMMABLE GATE ARRAY 1

1 hit Apply

Not Qualified 1

1 hit Apply

Yes 1

1 hit Apply

4.318 mm 1

1 hit Apply

5.25 V 1

1 hit Apply

4.75 V 1

1 hit Apply

Supply Voltage-Nom (1)

5 V 1

1 hit Apply

NO 1

1 hit Apply

CMOS 1

1 hit Apply

Temperature Grade (1)

OTHER 1

1 hit Apply

PIN/PEG 1

1 hit Apply