Parametric results for: XC7S50-2FTGB196I under Field Programmable Gate Arrays

All Filters Clock Frequency-Max Combinatorial Delay of a CLB-Max JESD-30 Code JESD-609 Code Length Manufacturer Number of CLBs Number of Inputs Number of Logic Cells Number of Outputs Number of Terminals Operating Temperature-Max Operating Temperature-Min Organization Package Body Material Package Code Package Equivalence Code Package Shape Package Style Part Life Cycle Code Programmable Logic Type Rohs Code Seated Height-Max Supply Voltage-Max Supply Voltage-Min Supply Voltage-Nom Surface Mount Temperature Grade Terminal Finish Terminal Form

1.286 GHz 1

1 hit Apply

Combinatorial Delay of a CLB-Max (1)

1.05 ns 1

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S-PBGA-B196 1

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e3 1

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15 mm 1

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Manufacturer (1)

AMD Xilinx 1

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Number of CLBs (1)

4075 1

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Number of Inputs (1)

250 1

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Number of Logic Cells (1)

52160 1

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Number of Outputs (1)

250 1

1 hit Apply

196 1

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100.0 °C 1

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-40.0 °C 1

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4075 CLBS 1

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PLASTIC/EPOXY 1

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LFBGA 1

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BGA196,14X14,40 1

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Package Shape (1)

SQUARE 1

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GRID ARRAY, LOW PROFILE, FINE PITCH 1

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Transferred 1

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Programmable Logic Type (1)

FIELD PROGRAMMABLE GATE ARRAY 1

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Yes 1

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1.55 mm 1

1 hit Apply

1.05 V 1

1 hit Apply

950 mV 1

1 hit Apply

Supply Voltage-Nom (1)

1 V 1

1 hit Apply

YES 1

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Temperature Grade (1)

INDUSTRIAL 1

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MATTE TIN 1

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BALL 1

1 hit Apply