Parametric results for: XCV50-4CS144I under Field Programmable Gate Arrays

All Filters Clock Frequency-Max Combinatorial Delay of a CLB-Max JESD-30 Code JESD-609 Code Length Manufacturer Moisture Sensitivity Level Number of CLBs Number of Equivalent Gates Number of Inputs Number of Logic Cells Number of Outputs Number of Terminals Organization Package Body Material Package Code Package Equivalence Code Package Shape Package Style Part Life Cycle Code Pbfree Code Peak Reflow Temperature (Cel) Programmable Logic Type Qualification Status Rohs Code Seated Height-Max Supply Voltage-Max Supply Voltage-Min Supply Voltage-Nom Surface Mount Technology Terminal Finish Terminal Form

250 MHz 1

1 hit Apply

Combinatorial Delay of a CLB-Max (1)

800 ps 1

1 hit Apply

S-PBGA-B144 1

1 hit Apply

e0 1

1 hit Apply

12 mm 1

1 hit Apply

Manufacturer (1)

AMD Xilinx 1

1 hit Apply

3 1

1 hit Apply

Number of CLBs (1)

384 1

1 hit Apply

Number of Equivalent Gates (1)

57906 1

1 hit Apply

Number of Inputs (1)

94 1

1 hit Apply

Number of Logic Cells (1)

1728 1

1 hit Apply

Number of Outputs (1)

94 1

1 hit Apply

144 1

1 hit Apply

384 CLBS, 57906 GATES 1

1 hit Apply

PLASTIC/EPOXY 1

1 hit Apply

TFBGA 1

1 hit Apply

BGA144,13X13,32 1

1 hit Apply

Package Shape (1)

SQUARE 1

1 hit Apply

GRID ARRAY, THIN PROFILE, FINE PITCH 1

1 hit Apply

Obsolete 1

1 hit Apply

No 1

1 hit Apply

240 1

1 hit Apply

Programmable Logic Type (1)

FIELD PROGRAMMABLE GATE ARRAY 1

1 hit Apply

Not Qualified 1

1 hit Apply

No 1

1 hit Apply

1.2 mm 1

1 hit Apply

2.625 V 1

1 hit Apply

2.375 V 1

1 hit Apply

Supply Voltage-Nom (1)

2.5 V 1

1 hit Apply

YES 1

1 hit Apply

CMOS 1

1 hit Apply

Tin/Lead (Sn63Pb37) 1

1 hit Apply

BALL 1

1 hit Apply