Parametric results for: xc7k325t-l2ffg900i under Field Programmable Gate Arrays

All Filters Combinatorial Delay of a CLB-Max JESD-30 Code JESD-609 Code Length Manufacturer Moisture Sensitivity Level Number of CLBs Number of Terminals Organization Package Body Material Package Code Package Shape Package Style Part Life Cycle Code Peak Reflow Temperature (Cel) Programmable Logic Type Rohs Code Seated Height-Max Supply Voltage-Max Supply Voltage-Min Supply Voltage-Nom Surface Mount Terminal Finish Terminal Form Combinatorial Delay of a CLB-Max (1)

610 ps 2

2 hits Apply

S-PBGA-B900 2

2 hits Apply

e1 2

2 hits Apply

31 mm 2

2 hits Apply

Manufacturer (2)

AMD 1 AMD Xilinx 1

2 hits Apply

4 2

2 hits Apply

Number of CLBs (1)

25475 2

2 hits Apply

900 2

2 hits Apply

25475 CLBS 2

2 hits Apply

PLASTIC/EPOXY 2

2 hits Apply

BGA 2

2 hits Apply

Package Shape (1)

SQUARE 2

2 hits Apply

GRID ARRAY 2

2 hits Apply

Active 1 Transferred 1

2 hits Apply

245 2

2 hits Apply

Programmable Logic Type (1)

FIELD PROGRAMMABLE GATE ARRAY 2

2 hits Apply

Yes 2

2 hits Apply

3.35 mm 2

2 hits Apply

970 mV 2

2 hits Apply

930 mV 2

2 hits Apply

Supply Voltage-Nom (1)

950 mV 2

2 hits Apply

YES 2

2 hits Apply

TIN SILVER COPPER 2

2 hits Apply

BALL 2

2 hits Apply