Parametric results for: xcv100e-7pqg240i under Field Programmable Gate Arrays

All Filters Clock Frequency-Max Combinatorial Delay of a CLB-Max JESD-30 Code JESD-609 Code Length Manufacturer Moisture Sensitivity Level Number of CLBs Number of Equivalent Gates Number of Inputs Number of Logic Cells Number of Outputs Number of Terminals Operating Temperature-Max Operating Temperature-Min Organization Package Body Material Package Code Package Equivalence Code Package Shape Package Style Part Life Cycle Code Pbfree Code Peak Reflow Temperature (Cel) Programmable Logic Type Qualification Status Rohs Code Seated Height-Max Supply Voltage-Max Supply Voltage-Min Supply Voltage-Nom Surface Mount Technology Terminal Finish Terminal Form

400 MHz 1

1 hit Apply

Combinatorial Delay of a CLB-Max (1)

420 ps 1

1 hit Apply

S-PQFP-G240 1

1 hit Apply

e3 1

1 hit Apply

32 mm 1

1 hit Apply

Manufacturer (1)

AMD Xilinx 1

1 hit Apply

3 1

1 hit Apply

Number of CLBs (1)

600 1

1 hit Apply

Number of Equivalent Gates (1)

32400 1

1 hit Apply

Number of Inputs (1)

158 1

1 hit Apply

Number of Logic Cells (1)

2700 1

1 hit Apply

Number of Outputs (1)

158 1

1 hit Apply

240 1

1 hit Apply

100.0 °C 1

1 hit Apply

-40.0 °C 1

1 hit Apply

600 CLBS, 32400 GATES 1

1 hit Apply

PLASTIC/EPOXY 1

1 hit Apply

FQFP 1

1 hit Apply

QFP240,1.3SQ,20 1

1 hit Apply

Package Shape (1)

SQUARE 1

1 hit Apply

FLATPACK, FINE PITCH 1

1 hit Apply

Obsolete 1

1 hit Apply

Yes 1

1 hit Apply

245 1

1 hit Apply

Programmable Logic Type (1)

FIELD PROGRAMMABLE GATE ARRAY 1

1 hit Apply

Not Qualified 1

1 hit Apply

Yes 1

1 hit Apply

4.1 mm 1

1 hit Apply

1.89 V 1

1 hit Apply

1.71 V 1

1 hit Apply

Supply Voltage-Nom (1)

1.8 V 1

1 hit Apply

YES 1

1 hit Apply

CMOS 1

1 hit Apply

Matte Tin (Sn) 1

1 hit Apply

GULL WING 1

1 hit Apply