Datasheets
7201LA12PDG by:

512 x 9 AsyncFIFO, 5.0V, PDIP13/Tube

Part Details for 7201LA12PDG by Renesas Electronics Corporation

Overview of 7201LA12PDG by Renesas Electronics Corporation

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Part Details for 7201LA12PDG

7201LA12PDG CAD Models

7201LA12PDG Part Data Attributes

7201LA12PDG Renesas Electronics Corporation
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7201LA12PDG Renesas Electronics Corporation 512 x 9 AsyncFIFO, 5.0V, PDIP13/Tube
Pbfree Code Yes
Rohs Code Yes
Part Life Cycle Code Obsolete
Ihs Manufacturer RENESAS ELECTRONICS CORP
Part Package Code PDIP
Package Description DIP-28
Pin Count 28
Manufacturer Package Code PDG28
Reach Compliance Code compliant
ECCN Code NLR
HTS Code 8542320071
Samacsys Manufacturer Renesas Electronics
Access Time-Max 12 ns
Additional Feature RETRANSMIT
Clock Frequency-Max (fCLK) 50 MHz
Cycle Time 20 ns
JESD-30 Code R-PDIP-T28
JESD-609 Code e3
Length 36.576 mm
Memory Density 4608 bit
Memory IC Type OTHER FIFO
Memory Width 9
Moisture Sensitivity Level 1
Number of Functions 1
Number of Terminals 28
Number of Words 512 words
Number of Words Code 512
Operating Mode ASYNCHRONOUS
Operating Temperature-Max 70 °C
Operating Temperature-Min
Organization 512X9
Output Enable NO
Package Body Material PLASTIC/EPOXY
Package Code DIP
Package Equivalence Code DIP28,.6
Package Shape RECTANGULAR
Package Style IN-LINE
Parallel/Serial PARALLEL
Peak Reflow Temperature (Cel) 260
Qualification Status Not Qualified
Seated Height-Max 4.699 mm
Standby Current-Max 0.005 A
Supply Current-Max 0.08 mA
Supply Voltage-Max (Vsup) 5.5 V
Supply Voltage-Min (Vsup) 4.5 V
Supply Voltage-Nom (Vsup) 5 V
Surface Mount NO
Technology CMOS
Temperature Grade COMMERCIAL
Terminal Finish MATTE TIN
Terminal Form THROUGH-HOLE
Terminal Pitch 2.54 mm
Terminal Position DUAL
Time@Peak Reflow Temperature-Max (s) 30
Width 15.24 mm

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