Parametric results for: M312L5720CZ0-CA2 under DRAMs

All Filters Access Mode Access Time-Max Additional Feature Clock Frequency-Max (fCLK) I/O Type JESD-30 Code Manufacturer Memory Density Memory IC Type Memory Width Number of Functions Number of Ports Number of Terminals Number of Words Number of Words Code Operating Mode Operating Temperature-Max Operating Temperature-Min Organization Output Characteristics Package Body Material Package Code Package Equivalence Code Package Shape Package Style Refresh Cycles Supply Voltage-Nom (Vsup) Access Mode (1)

FOUR BANK PAGE BURST 1

1 hit Apply

Access Time-Max (1)

750 ps 1

1 hit Apply

AUTO/SELF REFRESH 1

1 hit Apply

Clock Frequency-Max (fCLK) (1)

133 MHz 1

1 hit Apply

COMMON 1

1 hit Apply

R-XDMA-N184 1

1 hit Apply

Manufacturer (1)

Samsung Semiconductor 1

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Memory Density (1)

19.3274 Gbit 1

1 hit Apply

DDR DRAM MODULE 1

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Memory Width (1)

72 1

1 hit Apply

1.0 1

1 hit Apply

1 1

1 hit Apply

184 1

1 hit Apply

268.4355 M 1

1 hit Apply

2.56E8 1

1 hit Apply

SYNCHRONOUS 1

1 hit Apply

70.0 °C 1

1 hit Apply

0.0 °C 1

1 hit Apply

Organization (1)

256MX72 1

1 hit Apply

3-STATE 1

1 hit Apply

UNSPECIFIED 1

1 hit Apply

DIMM 1

1 hit Apply

DIMM184 1

1 hit Apply

RECTANGULAR 1

1 hit Apply

MICROELECTRONIC ASSEMBLY 1

1 hit Apply

Refresh Cycles (1)

8192 1

1 hit Apply

Supply Voltage-Nom (Vsup) (1)

2.5 V 1

1 hit Apply