Parametric results for: hys64t128021hdl-5-a under DRAMs

All Filters Access Mode Access Time-Max Additional Feature Clock Frequency-Max (fCLK) I/O Type JESD-30 Code JESD-609 Code Manufacturer Memory Density Memory IC Type Memory Width Number of Functions Number of Ports Number of Terminals Number of Words Number of Words Code Operating Mode Operating Temperature-Max Operating Temperature-Min Organization Output Characteristics Package Body Material Package Code Package Equivalence Code Package Shape Package Style Refresh Cycles Supply Voltage-Nom (Vsup) Access Mode (1)

DUAL BANK PAGE BURST 1

2 hits Apply

Access Time-Max (1)

600 ps 2

2 hits Apply

AUTO/SELF REFRESH 1

2 hits Apply

Clock Frequency-Max (fCLK) (1)

200 MHz 2

2 hits Apply

COMMON 2

2 hits Apply

R-PDMA-N200 1 R-XDMA-N200 1

2 hits Apply

e3 1

2 hits Apply

Manufacturer (2)

Infineon Technologies AG 1 Qimonda AG 1

2 hits Apply

Memory Density (1)

8.5899 Gbit 2

2 hits Apply

DDR DRAM MODULE 2

2 hits Apply

Memory Width (1)

64 2

2 hits Apply

1.0 1

2 hits Apply

1 1

2 hits Apply

200 2

2 hits Apply

134.2177 M 2

2 hits Apply

1.28E8 2

2 hits Apply

SYNCHRONOUS 1

2 hits Apply

55.0 °C 1 65.0 °C 1

Min (°C) - Max (°C)

2 hits Apply

0.0 °C 2

2 hits Apply

Organization (1)

128MX64 2

2 hits Apply

3-STATE 2

2 hits Apply

PLASTIC/EPOXY 1 UNSPECIFIED 1

2 hits Apply

DIMM 2

2 hits Apply

DIMM200,24 2

2 hits Apply

RECTANGULAR 2

2 hits Apply

MICROELECTRONIC ASSEMBLY 2

2 hits Apply

Refresh Cycles (1)

8192 2

2 hits Apply

Supply Voltage-Nom (Vsup) (1)

1.8 V 2

2 hits Apply